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Puducherry Area, India India

Assistant Professor at Sri Manakula Vinayagar Engineering College

Education

Enthusiastic professional with 1 year +5 months experience as ASIC Verification Engineer. Have passion for learning and venturing into new ideas Good Knowledge in RTL coding using Verilog Expertise in Verification using System Verilog Experience in constrained based verification, assertion based verification and functional Verification Expertise in developing Verification environment for Module and SoC level using System Verilog/ Verilog, Shell scripting Specialties: 1. Programming Languages known - Verilog, System Verilog, C, C++, MATLAB. 2. Operating Systems - LINUX and Windows Tools Worked on Xilinix Modelsim Questa Sim Matlab