To continue being recognized as a Passionate, Creative and an Efficient Physical Design Engineer, and keep enhancing my skill set with each passing day..
Currently Working on 16 nm technology node.
- Good understanding and Practical Exposure to Block level Synthesis , Design Setup, Floor planning, APR (Placement, Clock Tree Synthesis, Routing), Physical Verification (DRC/LVS), Pre-layout & Post-layout STA, Chip finishing & DFM
- Practical exposure to Physical Design tools like IC Complier, Design Compiler, Primetime.
- Involved in Physical verification flow: DRC, LVS clean-up activities, Base layer and
Metal layer DRC fixes and make the design short / open free.
- Responsible in Eco ...
