Specialties: Strong background and experience in entire ASIC low-power design flow
Led designs for ARM SoC subsystems, drove specification, implementation, integration,
Verilog RTL, DV, Synthesis, STA, Scan Insertion, ATPG, CDC
in NCSim, VCS, debug with Debussy/verdi.
Experienced in multi-clock domain design architecture.
Familiar with SystemC concepts and System verilog testbench environment.
Extensive experience with most industry-standard EDA tools like Design Compiler, Formality, LEC, Verdi/Debussy, VCS, NCSim, ModelSim, 0-in,
Experience with test vectors, test vector generation and debug
Implemented and led designs on architecture and design of Applications processors on Digita...
