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Bengaluru Area, India India

Senior Design Con. at Wafer space

Electronics / Computer Hardware

• Experience in Place & Route, Timing closure, Physical Verification (block level) • Hands on experience in handling Place & Route and STA tools/Platform like SOC Encounter, IC Compiler, Talus (Magma), PrimeTime (Synopsys), ETS •Good Knowledge on Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Analysis • Good knowledge on PERL and TCL scripting • Ability to work independently as well as part of a team • Quick learner with Good analytical and problem solving skills • Always on the look to improve skills and grow with the organization Specialties: Cadence SoC Encounter, Synopsys ICC, Megma Talus, PrimeTime, ETS, perl, tcl.