SPECIAL AREA OF EXPERTISE:
Hands-on experience of full-chip (includes digital and analog parts) netlists with Cadence and Synopsys tool flows. Simulations are implemented with transistor level netlists, which guarantees that exactly same netlist is simulated, which is sent to the fab!
1. Cadence AMSDesigner and Synopsys XA (former HSIM) flows in transient analysis domain:
o State-machinery operation like full-chip power up/down functionality
o Signal path functionality
o Biasing (I & V) condition checks
o Clock delivery
o PUP & POR-circuit functionality
o IO-ring functionality
o Delay path analysis
o JTAG and boundary scan operation check
2. Synopsys CircuitChecker flow in static ...