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Editor's Notes

1. Чтение инструкции и её декодированиеПоиск всех связанных данных, необходимых для обработки инструкцииОбработка инструкцииДоступ в память (2 тактовая инструкция)Запись результатов
2. 32 битные инструкции: ветвления и условного выполнения
3. Состаяние процессора переключается спец битом (24й)ARM CPSR (Current Program Status Register). The 'T'-bit must be cleared and the 'J'-bit set.
4. Первый арм проц с поддержкой виртуализации
5. The introduction of Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memoryPerformance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. Caches are 32KB for instruction and 32KB for data. Also providing the option for cache coherence for enhanced inter-processor communication or support of rich SMP capable OS for simplified multicore software developmenCoreLink CCN-504 extends the capabilities of your SoC. Up to 16 cores on the same silicon die are possible with this fully-coherent, high-performance many-core solution. With up to 1TB/s of system bandwidth, and support for large L3 caches, SoC designers can address the needs of networking, server, and other enterprise-class devices.
6. Pipeline depth:A15 15A9 8
7. A53 – 64bit A7A57 – 64bit A15
8. In-order processor
9. Стратегия, поддержание закона Мура
10. Front-end:32KB, 8-way set associative, first-level instruction cache,Branch prediction units and ITLB,Two instruction decoders, each can decode up to one instruction per cycle.JEU – jump execution unitAGU - Address Generation UnitTLB – Translation Lookup Buffer (Для перевода виртуальных адресов в физические.Физические адреса затем используются для обращения в кэш данных)PMH - Page Miss Handler (Virtual->Physical Translation)BIU — Bus Interface Unit контроллеры шины и L2;The memory execution sub-system (MEU) can support 48-bit linear address for Intel64 Architecture, either 32-bit or 36-bit physical addressing modes. The MEUprovides:• 24KB first level data cache,• Hardware prefetching for L1 data cache,• Two levels of DTLB for 4KByte and larger paging structure.• Hardware pagewalker to service DTLB and ITLB misses.• Two address generation units (port 0 supports loads and stores, port 1 supportsLEA and stack operations)• Store-forwarding support for integer operations• 8 write combining buffers.The bus logic sub-system provides• 512KB, 8-way set associative, unified L2 cache,• Hardware prefetching for L2 and interface logic to the front side bus.
11. Большинство инструкций переводятся в 1 мюопс5% инструкций требуют разбивки на мюопсыРазбивка на мюопсы не дает особых преимуществ на in order