Electronic fault isolation of FPGA devices.
Translate FPGA defect to a physical location using IC layout tool and comunicate defect location on to Failure Analysis Engineer.
Report Writing.
Oracle based data analysis.
Calibration and Installation of TEM microscopes.
Training of new employees.
Operated in class 100 clean room environment to meet GMP standards.
Worked in large and small groups and also on my own initiative to meet production/customer goals.
We鈥檝e updated our privacy policy so that we are compliant with changing global privacy regulations and to provide you with insight into the limited ways in which we use your data.
You can read the details below. By accepting, you agree to the updated privacy policy.
