1.Good knowledge in ASIC and FPGA design flow.
2.Good knowledge in writing RTL and testbenches
3.Good knowledge in verification methodologies.
4.Good experience in industry standard EDA tools for front end design in verification (XILINX,CADENCE,RIVIERA PRO)
5.Projects undertaken
a). Design of a 16脳9 Router for SOC designs using verilog
b).Design of efficient golay encoder for deep space missions using verilog
c).Design of a SMART prepaid ENERGY METER for electricity theft detection.
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