Team leader of circuit/layout designers exploring early stage of DRAMs (dynamic random access memories) from 16k-bit to 4M-bit generations. Analyzed and solved the circuit troubles caused by alpha-particle induced soft errors in DRAMs, built and commercialized the 1st CMOS dual-port DRAMS for graphics applications and proposed several kinds of 3-dimensional memory structures.
Group manager novel circuit concepts promoting commercialization of such devices as SOI (Silicon-On-Insulator), BiCMOS and embedded DRAM logics.
Senior manager coordinating and promoting collaborative research between semiconductor industry and universities in US and Japan.
Guest professor or visiting lecturer ...
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