-- Good hands on RTL coding (Verilog HDL)
-- Develop MBIST Generators which is responsible for testing the embedded memories and doing a repairability analysis.
-- Worked on RTL Synthesis and have knowledge on Static Timing Analysis (STA)
-- Good knowledge and experience in using VCS, ModelSim, NCSim, DC, Formality, Tetramax, Spyglass.
-- Involved in developing the test plans for Validation of the different memories using the MBIST(Memory BUILT IN SELF TEST)
-- SHELL scripting.
-- Worked on VLSI tools [ModelSim, Synopsys Design Compiler (DC), PrimeTime (PT), ncsim,Modelsim]
- Worked on FrontEnd-Kit (An Internal tool for different Validation flows) Validation.
- Worked on Automation of ...