Area Of Interest
SoC, IP Core Designing,
Multi-Core Processor Designing
RTL verilog(HDL) codding
Design Verification
FPGA Base DSP Algorithm Designing,
DSP Design at DSP Kit using CCS 3.1, Matlab Simulink
Good knowledge of RF Planing,GSM,GPON,CDMA,Fiber Optics
Specialties: C,C++,MATLAB,Verilog RTL,ANSI C,Linux operating System,
Verilog Pro Xilinx(ISE 11, acellDSP,system genrator), CCS 3.1 Modelsim 6.5, Real time debugging using ChipScop
,FPGA digital signal processing,
electronics,operating systems, programming,
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