Passionate,Innovative and hard working engineer with an expertise in full ASIC design flow cycle and hands on experience in design verification methodologies. Currently, looking for an entry level job opportunity for Fall 2013.
Specialities :
鈥� SOC Design Flow(RTL coding to GDSII flow), logic synthesis, static timing analysis, custom statdard library generation(.lib), Floor planning, manual place and route.
鈥� Experience on Verification methodologies - ATPG/Scan, BIST with good debugging skills.
鈥� Proficient in C/C++ programming, Perl and Unix Shell Scripting
SKILL SET :
EDA Tools : Cadence, Synopsys, Primetime, Verdi...
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