11.5 Years of Experience in VLSI-ASIC Design
Functional Verification Manager for SOC/IP verification teams
Lead a team on SOC verification for many multi-million gate sub 28nm SOC
Full Chip SOC Verification
Low power management verification(PARTL,PAGLS)
LTE Thin Modem SoC verification experience
Multimedia Apps Processor SOC verification experience
Expertise in Interconnect verification
IP level validation in FPGA
Perfomance management in SOC
SPYGLASS/LEC
Analog & Mixed signal verification (AMS)
Formal Verification using Jasper,QuestaFormal
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