CORE COMPETENCY
>13 months of experience in ASIC design and verification
飩� Hands on Experience in System Verilog, Verilog
飩� Good knowledge of ASIC and FPGA Design flow.
飩� Good knowledge of IC Fabrication process.
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飩� Extensive experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM.
飩� Very good knowledge in verification methodologies (UVM).
飩� Experience in using industry standard EDA tools for the front-end design and verification
飩� Ability to contribute and work in a team.
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