Hands on Experience with ASIC design tool such as Design compiler(synopsys DC),ICC compiler(Synopsys ICC),Prime time compiler(synopsys PT),formal verification(synopsys Foramality).
-> Good understanding of CMOS and logic design.
-> Well versed with verilog-HDL to write synthesizable code and self checking Test-benches.
-> familiar with Tcl and PERL scripting.
-> Good knowledge on STA concept.
-> Good knowledge on formal verification(LEC check)
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