6 Years of Industry Experience in ASIC/IC design with extensive knowledge in STA, Synthesis, Low Power Design using CPF/UPF, Logic equivalence checks, Low Power Checks and Physical Design.
Experience in Detail:
- Creating design Constraints for complex SOC鈥檚 with > 250 clocks.
- Timing closure for full chip hierarchical designs (>20M gates).
- Hierarchical Synthesis (Both logic and Physical) for Multi Million Gate designs.
- Creating CPF/UPF for Low Power designs.
- Block Level DFT implementation and preparing the etchecker_command for the same.
- Physical Design: Executed PD till routing stage on two of the designs.
- Improving the clock tree spec file for better Skew & QOR and creating...
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