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Hyderabad Area, India, Karnataka India

R&D Engineer, Sr I:: Synopsys India Pvt Limited

Electronics / Computer Hardware

Worked on RF(Register File 2 port) and PDP(Pseudo Dual Port) memories. Experience with circuit techniques like power gating, clock gating,write assist, level-shifter Characterization of Critical paths, race conditions, STA and .lib generation(pin timing) Good Knowledge on memory compiler development cycle Knowledge of EM, IR drop, NBTI effects, SNM, WNM, Cell current, Standby current, data retention. Creation of Verilog Front-end Views including behavioral, power, ATPG and Behavioral models; ESPCV Noise, EMIR, Totem flows Placement File coding for Memory Compiler Statistical tolerance analysis(RSS, MPP, Monte-Carlo, PC6)