DPDK Acceleration with Arkville
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Arkville is a software and FPGA IP core combination that provides DPDK packet acceleration. The Arkville DPDK PMD software runs on the GPP and interfaces with the Arkville FPGA IP core to enable zero-copy packet transfers between the GPP and FPGA. This achieves high throughput over 150Gbps and low latency of 1.25us round trip time. Arkville can be used in smart NICs, network appliances, and DPDK accelerators to efficiently move packets between DPDK and FPGA hardware using AXI interfaces.
![Roadmap: 17.08
19息2017 Atomic Rules LLC
August 2017
Support for DPDK 17.08
Support for Vivado 2017.2
Examples include Atomic Rules TimeServo[1]
Timestamps from MAC to DPDK metadata
[1] TimeServo is a separate IP product that may be purchased
from Atomic Rules.](https://image.slidesharecdn.com/atomicrules-arkvilledpdkacceleration-170424112844/85/DPDK-Acceleration-with-Arkville-19-320.jpg)
DPDK Acceleration with Arkville
- 1. Arkville DPDK Acceleration Shep Siegel, CTO Atomic Rules LLC 1息2017 Atomic Rules LLC Shepard.Siegel@atomicrules.com Arkville DPDK Acceleration 2017-08-08
- 2. AR Background Providing FPGA Design Services since 2008 Contributions to numerous Open-Source Projects Began augmenting services with IP Core products UDP Offload Engine (2014) Arkville DPDK-Aware Data Mover (2016) TimeServo FPGA System Timer (2017) Small, but steadily growing Currently nine EE/CS engineers across North America Passed $1M in Services in CY2015 Differentiation with Tools and Methodology Broad and Agnostic set of Partners Growing set of Recurring Customers and Clients 2息2017 Atomic Rules LLC
- 3. Arkville: A DPDK Packet Conduit 3息2017 Atomic Rules LLC
- 4. Arkville: Why? DPDK First Not an Afterthought or Adaptation Both Higher Throughput and Lower Latency DPDK Aware Push GPP cycles to specialized FPGA RTL gates Zero-Copy GPP Driver = Lowest Possible Overhead DPDK Acceleration Certain workloads are better in RTL gateware Arkville enables a Software-First approach 4息2017 Atomic Rules LLC
- 5. Arkville: Where? Arkville is used as a building-block component in products and solutions such as Smart-NIC Devices Network Appliances DPDK Accelerators Anywhere there is the need to efficiently exchange data between DPDK-mbufs and AXI FPGA gates 5息2017 Atomic Rules LLC
- 6. Smart-NIC 6息2017 Atomic Rules LLC 6 Any Rate ENET MAC NIC H/W Offload RTL IP Arkville AXI HW Arkville DPDK PMD SW DPDK Applications GPP SW PCIe FPGA GPP AR Arkville HW/SW DPDK SW API AXI HW API
- 7. Network Appliance 7息2017 Atomic Rules LLC 7 Any Rate ENET MAC Appliance RTL IP Arkville AXI HW Arkville DPDK PMD SW Appliance GPP SW PCIe FPGA GPP AR Arkville HW/SW DPDK SW API AXI HW API
- 8. DPDK Accelerator 8息2017 Atomic Rules LLC 8 AXI Accelerator RTL IP from HLS, OpenCL, BSV Arkville AXI HW Arkville DPDK PMD SW DPDK Applications or fd.io/VPP Nodes GPP SW PCIe FPGA GPP AR Arkville HW/SW DPDK SW API AXI HW API
- 9. Arkville: How? A Software and Gateware Combination: Arkville 17.05 DPDK Poll Mode Driver (DPDK PMD) Open-Source BSD from The Linux Foundation http://dpdk.org/doc/guides/nics/ark.html Arkville 17.05 FPGA RTL IP Core (AXI RTL IP) Atomic Rules sells named-project and site-based licenses http://www.atomicrules.com/arkville Arkville performs the data-mover work for products and solutions that require FPGA/GPP communication 9息2017 Atomic Rules LLC
- 10. High-Level Block Diagram 10息2017 Atomic Rules LLC
- 11. Over 150 Gbps Throughput 11息2017 Atomic Rules LLC
- 12. 1.25 us RTT/2 Latency 12息2017 Atomic Rules LLC
- 13. About Arkville Latency By Itself, Arkville contributes just 100ns to the ingress/egress latency budget Software: Arkville DPDK PMD: Constant Time 20ns per packet (e5-2630v4) Zero-Copy No GPP Cycles moving packet data! Hardware: Arkville AXI RTL IP: 20 Cycles at 250 MHz = 80ns + 4ns/64B Deterministic, store-and-forward 13息2017 Atomic Rules LLC
- 14. No memcpy() Arkville is unique among DPDK Poll Mode Drivers in that packet data is landed zero-copy exactly in user-land memory Zero CPU cycles are used by net/ark PMD for packet data movement Result is a constant O(1) time for all packets that fit in a single mbuf (See next slide) More CPU cycles for your application Fewer CPU cores needed for same amount of work 14息2017 Atomic Rules LLC
- 15. Zero-Copy DPDK Driver 15息2017 Atomic Rules LLC
- 16. Zero Packets Dropped 16息2017 Atomic Rules LLC
- 17. Questions / Feedback Is FPGA acceleration of packet-based DPDK workloads of interest? Are there specific challenges you are facing that perhaps Arkville will help solve? How do you measure success? Do you have a target platform in mind? How would you like to get started? 17息2017 Atomic Rules LLC
- 18. Summary and Thank You! 18息2017 Atomic Rules LLC Arkville is a GPP/FPGA DPDK-Aware Conduit Software is an Open-Source DPDK Poll Mode Driver RTL IP Core Gateware is sold by Atomic Rules Named-Project and Site-Based Licenses are Available Arkville is Agnostic Support for Contemporary FPGA Devices Support for COTS and Custom FPGA Boards Arkville is Supported Ongoing developments to the DPDK/LF Community AR offers both HW and SW services and support
- 19. Roadmap: 17.08 19息2017 Atomic Rules LLC August 2017 Support for DPDK 17.08 Support for Vivado 2017.2 Examples include Atomic Rules TimeServo[1] Timestamps from MAC to DPDK metadata [1] TimeServo is a separate IP product that may be purchased from Atomic Rules.
- 20. Roadmap: 17.11 20息2017 Atomic Rules LLC November 2017 Support for DPDK 17.11 Support for Vivado 2017.3 Available with 16 RX Queue-Pairs Next-Generation MBUF Prefetcher Still Zero-Copy and Low-microsecond Twire-to-user Expanded DPDK examples for VPP and OVS
- 21. Backup Material 21息2017 Atomic Rules LLC
- 22. Core Beliefs and Axioms 22息2017 Atomic Rules LLC Our Customers Success is Key Separation of Concerns Divide and Conquer Automate or Die Write Things Once Interface Before Implementation Functional Correctness First Performance Correctness Improved Iteratively Components Must Compose Components Must Work as Expected IP Should be Portable, Vendor-Agnostic if possible
- 23. Partner Roster 23息2017 Atomic Rules LLC 25G / 50G Ethernet Consortium 25-50-100 Ethernet Alliance Accellera/OCP-IP Community Member Amazon F1 Instance Partner ARM Connected Community Member BittWare Solution Partner Bluespec Technology Partner DPDK Project Corporate Member FPGA, FCCM and FPL F Conference Sponsors Intel Network Builders Linux Foundation Corporate Member MathWorks Connections Partner NetFPGA Infrastructure Developer OpenCPI Infrastructure Developer P4 Language Consortium Member PCI-SIG Corporate Member VITA Trade Association Member Xilinx Alliance Member Partner
- 24. 100 GbE DPDK Offload 24息2017 Atomic Rules LLC