Complete Owership on the block to Chip level floor planning, layout of basic blocks and to top level, layout of pad ring and ESD layout with DRC,DFM & LVS clean with Parasitic Extraction.
- Designing area efficient layouts
- Designing layout in advanced CMOS nodes (14nm and above)
- Understanding of analog and RF circuits specific layout issues/techniques such as:
* matching techniques
* crosstalk isolation techniques
* reliability issues
- Experience using extraction and verification tools
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