Personal Information
Organization / Workplace
Paris Area, France France
Occupation
Design Engineer at ERTE, BOWENFR
Industry
Telecom / Mobile
About
More than 8 years of working experience in DSP/FPGA design; FPGA implementation of IPs using VHDL/Verilog/NGC on AXI4lite/PLB bus; implementation, and validation of HDL reference designs associating microblaze, UART, SPI, I2C, Ethernet; Understanding of PHY layer of LTE, 802.11, ZigBEE; Strong experience of using Xilinx Vivado, ISE, SDK, and Modelsim, for simulations and implementations; Acquaintance of hardware architecture definitions; Understanding of using Orcad capture for Schematic developement of PCBs; Acquaintance of digital radio front-end AD9361/9364, LMS6002, high speed ADC AD6676, and clock cards HMC7044; Compling linux based kernel for single board computers (Raspberry, And...
Contact Details
Users following Vaibhav Bhatnagar