Personal Information
Organization / Workplace
Mirialguda Area, India India
Occupation
Design and Verification Engineer
Industry
Design
About
RTL coding in Verilog or VHDL, RTL integration, etc
Digital module design experience
Knowledge: RTL Coding, FSM based design, Simulation,
Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis, ABV
Verification background, familiarity with Clock Domain Crossing Checks, etc
Test benches in SystemVerilog , Coverage Driven Verification,Functional Verification
Very good knowledge in verification methodologies(UVM)
Knowledge of ARM subsystem, I2C blocks, UART,SPI,AHB, AXI Bus, Ethernet 10Gbps and PCIe.
Scripting knowledge in Perl and Shell
Experience in using industry standard EDA tools for the front-end design and verification
EDA Tools like Model sim, Questa and Xili...
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