Recent MSEE Graduate, looking for full time opportunities in Digital Design and Verification.
About
MSEE graduate with the profile focusing on Digital VLSI. Designed and synthesized important projects in Digital Design using Verilog HDL and also developed industry standard Verification projects using SystemVerilog. Developed a profile comprising of Digital Design and Design Verification skills during the academic career with additional knowledge of scripting language like PERL and various professional simulation and synthesis tools like QuestaSim, Synopsys VCS, XlLINX, etc. Curious and enthusiastic to learn new technologies and always try to quickly adapt to the new environment.
Seeking an Internship or Entry Level/Mid Senior Level Full Time opportunity in field related to Digital/ASIC ...
We鈥檝e updated our privacy policy so that we are compliant with changing global privacy regulations and to provide you with insight into the limited ways in which we use your data.
You can read the details below. By accepting, you agree to the updated privacy policy.
