Over four year experience in Synthesis, MVRC, Formality, Lint, CDC, tcl/perl scripting.
Hands on experience on Placement and routing, STA etc
Specialties:
Lead Chip implementation teams
Full chip RTL integration.
Linting
UPF Development for Multi Power/Voltage Domain Chips
Synthesis (Multi Power/Voltage Domain chips with UPF Flow) for SoC and Block level.
Constraints Development and Timing Closure (STA)
TCL/PERL scripting.
Formal verification: MVRC, LEC for complex SoC.
Test Vector Development and simulation.
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