Arpita offers 1+ years of experience in Analog layout. Her expertise in Physical verification domain has led to effective work delivery to Top US-based semiconductor firms (Feescale semiconductors currently NXP) and Uhnder.
She is well versed with understanding the verification and layout problems & tools to solve them.She has done hands on activities on 16nm,28nm and 90nm nodes. She has done floor planning for Opamp and some standard cells and also worked on voltage and bias regulator and Rx blocks did drc,lvs and mrc checks and generated gds for XOR checks.
Arpita has strong interpersonal and communication skills. She has developed healthy relationships with the team and support st...
We鈥檝e updated our privacy policy so that we are compliant with changing global privacy regulations and to provide you with insight into the limited ways in which we use your data.
You can read the details below. By accepting, you agree to the updated privacy policy.
