Currently working on Deep Learning models with the Green-IC group in Electronics and computer engineering department at NUS.
Enthusiastic about Deep learning and its hardware Implementation.
Three years experience in the Semiconductor industry in architecture, microarchitecture, rt design and implementation.
Worked as a second POC( point of contact) in the SOC design team as a NoC designer for 6 months and working as the first POC in the SoC design team as a NoC designer for 1 year now.
Hands-on experience in many aspects of RTL design such as Verilog Designing,Synthesis, timing analysis, Performance analysis of the SoC and Integration of the IP in the SOC. Hand on experience with PPA ...
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