8 Years of experience in ASIC Physical Design (Netlist2GDS) at 20/28/32/45/ Nanometer Technology Node.
1. Hands on Experience on Full Netlist2GDS flow at 20/28/32/45nm Technology Node.
2. Worked on High Speed/Graphics/Modem, Low Power, Multi Power Domain and Multi Mode Multi corner (MMMC) Flow.
3. Good understanding of Placement/Routing Congestion Removal Techniques.
4. Knowledge of Fixing Sig/Clock Max Tran/Max Cap and ESD_C2I/EM/Xtalk Violations
5. Hands on Experience of Writing Timing Ecos, PTSI what-if-analysis.
6. Good Understanding of DRC/LVS Signoff checks.
Expert in Floorplanning, Area Reduction methodology
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