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jagsshete

Jagdish Shete

Personal Information
Organization / Workplace
Ichalkaranji Area, India India
Occupation
RTL Verification Engineer
About
--working as Verification Engineer in LinkedLoop Technology Pune since 1 year --Worked as Assistant Professor in Walchand College of Engineering Sangli . --Project experience of Digital System Design by using VLSI approach based on FPGA platform. --Hands on experience of Verilog and System Verilog Programming --Instructor in-charge of subject Circuit Theory , Scientific Computation Tools , Simulation Tools --Mini project coordinator for entire batch of TY B.TECH during year 2014-16. --Hands on experience on ALTIUM and CADSTAR tools used in PCB design technology. --Hands on experience on PROTEOUS , MULTISIM and MATLAB simulation tools. --Hands on experience on LabVIEW Scient...
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