Personal Information
Organization / Workplace
Bengaluru Area, India India
Occupation
Design Manager at Mirafra Technologies
Industry
Electronics / Computer Hardware
About
• Experience in Verilog RTL based IP design, simulation, synthesis and verification
• Experience in SOC integration
• Experience in AMBA/I2C bus protocols, MIPI, SD/MMC protocols.
• Synthesis of FPGA/ASIC designs
• Gate level netlist and timing simulations
• Functional pattern generation and re-simulation
• FPGA/Post silicon validation
• DC/RC synthesis scripts
• LINT checks
• Advance CDC checks
• Non-Resettable flop checks
• RMM guidelines and synthesis techniques
• Verilog behavioral modeling
Specialties: Tools:-
Simulation - ModelSim, NC Sim, VCS, NC-Verilog and Aldec’s Active HDL,
Synthesis - Design Compiler, RTL Compiler, Leonardo Spectrum, Synplify Pro a
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