Memory Layout Design Engineer at DXCorr Design Inc.
Industry
Electronics / Computer Hardware
About
Excellent Knowledge in Memory Layout Architecture Design.
Excellent Knowledge in ASIC Design Flow and Full Custom Flow.
Have a experience in memory compiler like SRAM, ROM, and Standard cell design in various technology nodes : 28nm, 22nm FDSOI, 14nm FINFET.
Works on Various blocks like Bitcell, I/O cell, Control and Decoder.
Excellent Skill to debug DRC, LVS, ERC, DFM, EM/IR issues.
Hands on experience with Cadence Virtuoso, Voltus-fi and Mentor Graphic Calibre.
Concise understanding of logic design and CMOS concepts.
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