A Post Graduate in VLSI design technology and comes with five years of industry experience in areas of electronic design validation and EDA tools/methodologies for ASIC IPs/SoCs and CPU products
Specialties: Software Language/Platforms: C, Perl, Shell, gdb, UNIX/LINUX, Windows
HDLs/HVLs(hardware design): Verilog/System Verilog, Specman e
EDA tools: Synopsys VCS, Cadence Specman, Novas Verdi, Mentor Modelsim/0-in, Bitkeeper, RCS, Clearcase, FPGAs Xilinx ISE, Altera Quartus, SPICE