飪� Hands on experience in deep sub micron technologies(40nm,45nm,55nm,60nm,90nm,130nm)
飪� Process technologies: UMC,TSMC,L4LP,SMIC
飪� Layout Design for various blocks(RX,TX,,SERDES,V2I,PLL,BIAS)
飪� Physical verification (DRC, LVS and PEX) on Calibre
飪� Matching of Devices (Common centroid & Inter digitization)
飪� Power/ground structure, block placement and layout floor planning
飪� Prevention of latch-up possibilities & notchfree layouts
飪� Creation of PCELL
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