Work on all aspects of physical design including synthesis, involved floor planning & power plan,
Good placement by improving congestion & timing,
Well in CTS building by meeting targets like skew & insertion delay,
Routing issues like Cross-talk & EM,
Physical verification(DRC,LVS,ERC).
Clear understanding and command over all aspects of physical design.
Hands on experience on PnR Synopsys IC Compiler / Cadence SoC Encounter.
Sign-off analysis like STA for fixing Setup & Hold timing violations.
Signal Integrity issues like Cross-talk & Electro-Migration.
IR-Drop Analysis ,by using Low-power design techniques.
Good knowledge in UNIX & scripting using CSHELL,PERL&TCL.
Friendly working o...
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