I currently work at the Reconfigurable Computing Laboratory at Iowa State University, where I research ways to accelerate applications with FPGAs. Applications I have designed accelerators for include exact DNA alignment, sequential belief propagation, sparse matrix vector multiplication and k nearest neighbors.
FPGAs are the chameleons of the chip world. To accelerate an application I create a processor design. Electronic design tools then turn this processor design into a schematic the FPGA can read and then emulate the processor. From my view, I now have the processor I want. (Although it's a bit slower than a processor made in a ASIC Fab.)
Contact Details
Tags
bag of wordstext classificationk-nnfpgafloating point compressionfzipconveyhigh performance reconfigurable computing
We鈥檝e updated our privacy policy so that we are compliant with changing global privacy regulations and to provide you with insight into the limited ways in which we use your data.
You can read the details below. By accepting, you agree to the updated privacy policy.
