 Having hands on experience in VLSI ASIC PnR Flow.
 Team Member in IC Compiler PnR Flow Development. Concentrated on CTS stage.
 Expertise in FloorPlan, CTS, Timing Closure & ECO Flow and Worked on MMMC Designs.
 Worked as team member in ACT (Advance Chip Builder Tool) Automation flow development & Developed Automation Flow for IC Compiler PnR Flow.
 Good Knowledge in scripting languages like shell, PERL, TCL & MAKE.
 Expertise in using Cadence Encounter, Synopsys IC Compiler & Prime Time tools.
 Basic Knowledge in Low Power Design Flow.