際際滷

際際滷Share a Scribd company logo

End of a trend

M
mml2000

Power consumption has become the limiting factor for increasing microprocessor performance. Multi-core processors offer a more power-efficient way to improve performance by utilizing multiple simpler cores instead of increasing clock speeds. This shift to multi-core architectures presents technical challenges for interconnects, operating systems, and software to take advantage of parallel processing.

1 of 17
Its over! The end of a 30 year trend in computing Miles Lewitt We are dedicating all of our future product development to This is a sea change in computing Paul Otellini (2005), President, Intel
Gordon Moore 2003 Another decade is probably straightforward... There is certainly no end to creativity. Bio: Currently Chairman Emeritus of Intel Corporation. Moore co-founded Intel in 1968, serving initially as Executive Vice President. He became President and Chief Executive Officer in 1975 and held that post until elected Chairman and Chief Executive Officer in 1979. He remained CEO until 1987 and was named Chairman Emeritus in 1997. Moore earned a B.S. in Chemistry from the University of California at Berkeley and a Ph.D. in Chemistry and Physics from the California Institute of Technology. He was born in San Francisco, Calif., on Jan. 3, 1929. He is a director of Gilead Sciences Inc., a member of the National Academy of Engineering, and a Fellow of the IEEE. Moore also serves on the Board of Trustees of the California Institute of Technology. He received the National Medal of Technology from President George Bush in 1990. 1965 Moores Law: The number of transistors incorporated in a chip will double every 24 months
Niklaus Wirth 1995 Software gets slower, faster than hardware gets faster" Bio: Professor of Computer Science at ETH (Federal Institute of Technology) in Zurich, Switzerland, from 1968 to 1999. His principal areas of contribution were programming languages and methodology, software engineering, and design of personal workstations. He has designed the programming languages Algol W (1965), Pascal (1970), Modula-2 (1979), and Oberon (1988), was involved in the methodologies of structured programming and stepwise refinement, and designed and built the workstations Lilith (1980) and Ceres (1986). He has published several text books for courses on programming, algorithms and data structures, and logical design of digital circuits. He has received various prizes and honorary doctorates, including the Turing Award (1984), the IEEE Computer Pioneer (1988), and the Award for outstanding contributions to Computer Science Education (acm 1987).
If the hardware ever stopped getting faster What would the impact be on developing and evolving software offerings?
Process Scaling Drives Transistor Count Process scaling enables feature size reduction by a factor of 0.7 every 24 months 592,000,000 2004 Intel Itanium 2 processor (9MB cache) 220,000,000 2002 Intel Itanium 2 processor 25,000,000 2001 Intel Itanium processor 42,000,000 2000 Intel Pentium 4 processor 9,500,000 1999 Intel Pentium III processor 7,500,000 1997 Intel Pentium II processor 3,100,000 1993 Intel Pentium processor 1,200,000 1989 Intel486 TM processor 275,000 1985 Intel386 TM processor 134,000 1982 Intel286 29,000 1978 8086 4.500 1974 8080 2,500 1972 8008 2,300 1971 4004 Transistors Year of Introduction Microprocessor
Uni-Processor Performance Performance = Instructions Per Clock * Clock Frequency Applying transistors to improve performance Reduce memory latency Cache architecture and size Increase instruction level parallelism Speculative execution Branch prediction Out of order execution Increased pipelining Additional execution units
1000x Performance Improvement Pentium 4 Processor 386 Processor May 1986 @16 MHz core 275,000 1.5 transistors 1.2 SPECint2000 August 2003 @3.2 GHz core 55 Million 0.13 transistors 1249 SPECint2000 17 years 200x 200x / 11x 1000x
1000X looks good! What is the Problem? Has Moores Law hit a wall? No transistor counts continue to be able to grow We have hit another wall Power Power consumption of desktop microprocessors has reached 130 watts Power = Capacitance * Voltage 2 * Frequency Contemporary microprocessor design deliver as much performance as possible while keeping power consumption reasonable
Influencing Power Consumption Through Design, Process and Environment Compare the 65nm Pentium 4 to the i486 Performance 8x Power consumption 38x The Pentium 4 processor spends 5 times the energy per instruction of the i486 (fabricated on the same process technology and operated at the same voltage) 1.3 31 (8.0) one core 1721 Specint2K (7.7) 2.167 GHz Core Duo 65 nm 1.33 86 (38.0) 1764 Specint2K (7.9) 3.6 GHz Pentium 4 65 nm 1.32 21 (7.0) 1429 Specint2K (5.4) 2.0 GHz Pentium M 90 nm 1.75 75.3 (23.0) 681 Specint2K (6.0) 2.0 GHz Pentium 4 180 nm 3.1 29.2 (9.0) 6.08 Specint95 (3.6) 150 MHz Pentium Pro 0.6 m 5 13 (2.7) 77.9 Specint92 (2.0) 66 MHz Pentium 0.8 m 5 4.9 (1.0) 39.6 Specint92 (1.0) 66 MHz i486 0.8 m Volts Power (normalized) Performance (normalized) Frequency Product Process
Why Multi-Core By spending the growing transistor budget on faster designs power consumption increases 5 times as fast as performance Deep pipelines Out of order structures Speculative execution By spending the growing transistor budget on multiple relatively simple cores power consumption increases approximately linearly with potential performance
Impact on Software Until recently, increasing uni-processor clock speeds and micro architectural improvements could be counted on to provide performance improvements for all software With multi-core hardware only the performance of highly multi-threaded applications will continue to see improvement Software has depended on this environment with annual performance boosts Tackle problems of increased complexity Compensate for programming at higher levels of abstraction More natural user interface This free lunch is over
Implications of Multi-Core In 2018 256 billion transistors 128 cores How successful will the efforts be to retool operating systems to effectively support a large number of cores Will shared memory architectures scale to support a large number of cores or will many cores result in a packet-based network for multi-core interconnect? What are the implications? How is a multi-core chip validated? Limited I/O prevents complete observe-ability Implies the need for chip self test, diagnosis and repair for cores, cache and glue logic
Software Complexity The move to multi-core enabled applications increases complexity Rewriting legacy code Software engineer training Increased debugging Avoid race conditions Avoid deadlocks Will software applications which continue to take on problems of increasing complexity successfully take advantage of multi-core processing power
Asymmetric Multi-Core Heterogeneous cores can deliver higher performance than homogenous cores at a given power budget Will present multiple additional operating system and application challenges
Virtualization, SOA and Multi-Core Drive a trend in data center to consolidate work loads on larger more power efficient servers Support for multiple different operating environments On low cost commodity servers Higher resource utilization Flexibility in resource allocation Reduce power and cooling costs Enable more cost effective development and test environments Flexibility from the easily reallocated resources to the as needed environments for development and test SOA services are designed to operate as distributed components and thus can easily leverage multicore servers
Summary Power consumption is now the limiting factor for micro-processor performance Multi-core processors use power more efficiently to achieve higher performance levels and thus are the future Due to multi-core, there are technical challenges ahead for interconnect, operating systems and applications. Parallel application software will become mainstream
Implications For software vendors: Need experience building applications for multi-core computing Data center strategy appropriately leverage of multi-core technology Software performance tuning increases in importance For computing Need to develop the algorithms, programming languages, compilers, operating systems, and architectures to support 1000 CPUs / chip

More Related Content

End of a trend

  • 1. Its over! The end of a 30 year trend in computing Miles Lewitt We are dedicating all of our future product development to This is a sea change in computing Paul Otellini (2005), President, Intel
  • 2. Gordon Moore 2003 Another decade is probably straightforward... There is certainly no end to creativity. Bio: Currently Chairman Emeritus of Intel Corporation. Moore co-founded Intel in 1968, serving initially as Executive Vice President. He became President and Chief Executive Officer in 1975 and held that post until elected Chairman and Chief Executive Officer in 1979. He remained CEO until 1987 and was named Chairman Emeritus in 1997. Moore earned a B.S. in Chemistry from the University of California at Berkeley and a Ph.D. in Chemistry and Physics from the California Institute of Technology. He was born in San Francisco, Calif., on Jan. 3, 1929. He is a director of Gilead Sciences Inc., a member of the National Academy of Engineering, and a Fellow of the IEEE. Moore also serves on the Board of Trustees of the California Institute of Technology. He received the National Medal of Technology from President George Bush in 1990. 1965 Moores Law: The number of transistors incorporated in a chip will double every 24 months
  • 3. Niklaus Wirth 1995 Software gets slower, faster than hardware gets faster" Bio: Professor of Computer Science at ETH (Federal Institute of Technology) in Zurich, Switzerland, from 1968 to 1999. His principal areas of contribution were programming languages and methodology, software engineering, and design of personal workstations. He has designed the programming languages Algol W (1965), Pascal (1970), Modula-2 (1979), and Oberon (1988), was involved in the methodologies of structured programming and stepwise refinement, and designed and built the workstations Lilith (1980) and Ceres (1986). He has published several text books for courses on programming, algorithms and data structures, and logical design of digital circuits. He has received various prizes and honorary doctorates, including the Turing Award (1984), the IEEE Computer Pioneer (1988), and the Award for outstanding contributions to Computer Science Education (acm 1987).
  • 4. If the hardware ever stopped getting faster What would the impact be on developing and evolving software offerings?
  • 5. Process Scaling Drives Transistor Count Process scaling enables feature size reduction by a factor of 0.7 every 24 months 592,000,000 2004 Intel Itanium 2 processor (9MB cache) 220,000,000 2002 Intel Itanium 2 processor 25,000,000 2001 Intel Itanium processor 42,000,000 2000 Intel Pentium 4 processor 9,500,000 1999 Intel Pentium III processor 7,500,000 1997 Intel Pentium II processor 3,100,000 1993 Intel Pentium processor 1,200,000 1989 Intel486 TM processor 275,000 1985 Intel386 TM processor 134,000 1982 Intel286 29,000 1978 8086 4.500 1974 8080 2,500 1972 8008 2,300 1971 4004 Transistors Year of Introduction Microprocessor
  • 6. Uni-Processor Performance Performance = Instructions Per Clock * Clock Frequency Applying transistors to improve performance Reduce memory latency Cache architecture and size Increase instruction level parallelism Speculative execution Branch prediction Out of order execution Increased pipelining Additional execution units
  • 7. 1000x Performance Improvement Pentium 4 Processor 386 Processor May 1986 @16 MHz core 275,000 1.5 transistors 1.2 SPECint2000 August 2003 @3.2 GHz core 55 Million 0.13 transistors 1249 SPECint2000 17 years 200x 200x / 11x 1000x
  • 8. 1000X looks good! What is the Problem? Has Moores Law hit a wall? No transistor counts continue to be able to grow We have hit another wall Power Power consumption of desktop microprocessors has reached 130 watts Power = Capacitance * Voltage 2 * Frequency Contemporary microprocessor design deliver as much performance as possible while keeping power consumption reasonable
  • 9. Influencing Power Consumption Through Design, Process and Environment Compare the 65nm Pentium 4 to the i486 Performance 8x Power consumption 38x The Pentium 4 processor spends 5 times the energy per instruction of the i486 (fabricated on the same process technology and operated at the same voltage) 1.3 31 (8.0) one core 1721 Specint2K (7.7) 2.167 GHz Core Duo 65 nm 1.33 86 (38.0) 1764 Specint2K (7.9) 3.6 GHz Pentium 4 65 nm 1.32 21 (7.0) 1429 Specint2K (5.4) 2.0 GHz Pentium M 90 nm 1.75 75.3 (23.0) 681 Specint2K (6.0) 2.0 GHz Pentium 4 180 nm 3.1 29.2 (9.0) 6.08 Specint95 (3.6) 150 MHz Pentium Pro 0.6 m 5 13 (2.7) 77.9 Specint92 (2.0) 66 MHz Pentium 0.8 m 5 4.9 (1.0) 39.6 Specint92 (1.0) 66 MHz i486 0.8 m Volts Power (normalized) Performance (normalized) Frequency Product Process
  • 10. Why Multi-Core By spending the growing transistor budget on faster designs power consumption increases 5 times as fast as performance Deep pipelines Out of order structures Speculative execution By spending the growing transistor budget on multiple relatively simple cores power consumption increases approximately linearly with potential performance
  • 11. Impact on Software Until recently, increasing uni-processor clock speeds and micro architectural improvements could be counted on to provide performance improvements for all software With multi-core hardware only the performance of highly multi-threaded applications will continue to see improvement Software has depended on this environment with annual performance boosts Tackle problems of increased complexity Compensate for programming at higher levels of abstraction More natural user interface This free lunch is over
  • 12. Implications of Multi-Core In 2018 256 billion transistors 128 cores How successful will the efforts be to retool operating systems to effectively support a large number of cores Will shared memory architectures scale to support a large number of cores or will many cores result in a packet-based network for multi-core interconnect? What are the implications? How is a multi-core chip validated? Limited I/O prevents complete observe-ability Implies the need for chip self test, diagnosis and repair for cores, cache and glue logic
  • 13. Software Complexity The move to multi-core enabled applications increases complexity Rewriting legacy code Software engineer training Increased debugging Avoid race conditions Avoid deadlocks Will software applications which continue to take on problems of increasing complexity successfully take advantage of multi-core processing power
  • 14. Asymmetric Multi-Core Heterogeneous cores can deliver higher performance than homogenous cores at a given power budget Will present multiple additional operating system and application challenges
  • 15. Virtualization, SOA and Multi-Core Drive a trend in data center to consolidate work loads on larger more power efficient servers Support for multiple different operating environments On low cost commodity servers Higher resource utilization Flexibility in resource allocation Reduce power and cooling costs Enable more cost effective development and test environments Flexibility from the easily reallocated resources to the as needed environments for development and test SOA services are designed to operate as distributed components and thus can easily leverage multicore servers
  • 16. Summary Power consumption is now the limiting factor for micro-processor performance Multi-core processors use power more efficiently to achieve higher performance levels and thus are the future Due to multi-core, there are technical challenges ahead for interconnect, operating systems and applications. Parallel application software will become mainstream
  • 17. Implications For software vendors: Need experience building applications for multi-core computing Data center strategy appropriately leverage of multi-core technology Software performance tuning increases in importance For computing Need to develop the algorithms, programming languages, compilers, operating systems, and architectures to support 1000 CPUs / chip