I am a digital IC designer who loves researching computer vision and image processing technology. I have engaged in ASIC design for 4 years, FPGA design for 2 years and implemented sensor interface, image signal processing (ISP), rectification, depth-map algorithm in several commercial products.
In some recent projects, I responsible for design multi-core DSP system bus (AXI/AHB/APB), the L1/L2 memory bus for vector processing and instruction cache for scalar core. I also worked with software team by coding on C/C++/ SystemC and providing simulator of DSP Platform for FW early evaluation.
As an enthusiastic engineer, I also love to learn scripting language (e.g., Ruby, Python) and verif...
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