* Good understanding of the CMOS Design, Digital Design, ASIC design flow.
* Expertise in Synthesis and Physical Design.
* Good knowledge in Static Timing Analysis and Cross Talk Analysis.
* Good Understanding in IR-DROP and OCV.
* Familiar with EDA Tools like :
Cadence SOC Encounter 鈥� Floor Planning, Place & Route, Clock Tree Synthesis and Physical Verification.
RTL Compiler- Logic Synthesis
* Scripting : TCL & perl
* Worked on Industry Standard Tools Like SoC Encounter, RTL Compiler, Assura,Virtuoso,NC Sim.
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