- 8+ years of experience as ASIC Physical Design Engineer.
- Implemented 13 full chips from Design Planning to Silicon.
- Worked on multiple tapeouts as a Design Consultant with Leading semiconductor design houses like Beceem, SiRF Technologies and In house designs on different technology nodes ranging from 45n to 130n.
- Contributed towards tapeout of several multi-million gate SOC designs using Atoptech, Magma, Cadence and Synopsys Flows.
Specialties: RTL-GDSII and Netlist-GDSII
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