4+ years of experience in IP / Block Level Verification.
Hands on experience in Verification Planning (Coverage Plan, SVA Plan, Testcase Plan)
Hands on experience of development of test bench environment & bring-up for sanity testing from scratch.
Experience in Constraint Random Verification, Coverage Driven Verification techniques.
TECHNICAL SKILLS:
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HDL /HVL Languages : VHDL, Verilog , System Verilog , SVA
Verification Methodologies : UVM1.1, UVM1.2, UVM RAL, OSVVM, OVM
Simulation Tools : Model SIM v10.0d, Questa SIM v10.2c, VCS-MX v10.9.3,
Cadence SimVision v12.2, Riviera-Pro v2014.06
Synthesis Tools : Xilinx ISE 13.1i, ALTERA Quar...