1. Good understanding of the ASIC and FPGA design flow
2. Extensive experience in writing RTL models in verilog HDL and testbenches in system verilog and UVM
3. Very good knowledge in verification methodologies
4. Experience in using industry standard EDA tools for the front end design and verification
5. Protocols :AMBA bridge AHB2APB, SPI, UART,Router
6. Verfication Methodologies : coverage Driven verification, Assertion Based Verification
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