6.5 years of Experience in ASIC Design and verification
鈥� Specification development from the customer requirements
鈥� Development of High-Level Architecture
鈥� Module division and work sharing
鈥� Developing eVc
鈥� Gate level simulations setup and debug
鈥� SoC level and Block level Integration
鈥� Design development and bug fixes
鈥� Support to verification team to get 100% coverage
鈥� Synthesis and timing closure
鈥� Exposure to complete ASIC design flow from requirements to bug-free RTL delivery
鈥� Developed many utilities using PERL
鈥� Expertise in Verilog, e(Specman), C, PERL, UNIX and Shell scripting
鈥� Received Spot Recognition Awards for all the projects I have worke...
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