9 Yrs of experience in Design and Verification of FPGA/ASIC based applications.
Experienced in RTL Design, Synthesis & Timing.
Experienced in bitfile verification.
Experienced in RTL Verification using System Verilog.
Experienced on different EDA tools(Synplify Premier,PrimTime,Certify,VCS,Verdi,Questa Sim,Model-Sim,Active-HDL)
Experienced in Testing the EDA tool using the TCL.
Experienced in development of Avionics communication protocols like ARINC429, ARINC818 for aircraft avionics (compliance to DO-254 standard).
Hands of experience on FPGA Design flow.
Working knowledge of AMBA Protocols(AXI,AHB,APB)
Working knowledge of DDR4 Sdram Controller.
Working knowledge ...