�ݺ�ߣshows by User: PankajSingh137

�ݺ�ߣshows by User: PankajSingh137 / http://www.slideshare.net/images/logo.gif �ݺ�ߣshows by User: PankajSingh137 / Wed, 09 Oct 2024 17:35:34 GMT �ݺ�ߣShare feed for �ݺ�ߣshows by User: PankajSingh137 Universal Chip interconnect Verification /slideshow/universal-chip-interconnect-verification/272299647 dvconindia-2024ucie-241009173534-64edc362
This presentation introduces a comprehensive verification methodology for Universal Chiplet Interconnect Express (UCIe) technology, addressing the intricate challenges inherent in multi-die system design. Our approach encompasses three critical domains: optimization of multi-die system verification, rigorous validation of automotive-grade UCIe IP, and enhancement of overall verification quality and efficiency. We demonstrate substantial improvements in verification throughput and silicon quality by employing advanced techniques such as in-depth performance analysis, inter-die transaction integrity verification, using a versatile SystemVerilog UVM-based environment. This integrated framework offers a scalable solution to the complex verification challenges presented by chiplet-based architectures, facilitating the development of more robust and efficient semiconductor designs in the post-Moore's Law landscape. We address current industry needs and anticipate future requirements in the evolving field of heterogeneous integration.]]>
This presentation introduces a comprehensive verification methodology for Universal Chiplet Interconnect Express (UCIe) technology, addressing the intricate challenges inherent in multi-die system design. Our approach encompasses three critical domains: optimization of multi-die system verification, rigorous validation of automotive-grade UCIe IP, and enhancement of overall verification quality and efficiency. We demonstrate substantial improvements in verification throughput and silicon quality by employing advanced techniques such as in-depth performance analysis, inter-die transaction integrity verification, using a versatile SystemVerilog UVM-based environment. This integrated framework offers a scalable solution to the complex verification challenges presented by chiplet-based architectures, facilitating the development of more robust and efficient semiconductor designs in the post-Moore's Law landscape. We address current industry needs and anticipate future requirements in the evolving field of heterogeneous integration.]]> Wed, 09 Oct 2024 17:35:34 GMT /slideshow/universal-chip-interconnect-verification/272299647 PankajSingh137@slideshare.net(PankajSingh137) Universal Chip interconnect Verification PankajSingh137 This presentation introduces a comprehensive verification methodology for Universal Chiplet Interconnect Express (UCIe) technology, addressing the intricate challenges inherent in multi-die system design. Our approach encompasses three critical domains: optimization of multi-die system verification, rigorous validation of automotive-grade UCIe IP, and enhancement of overall verification quality and efficiency. We demonstrate substantial improvements in verification throughput and silicon quality by employing advanced techniques such as in-depth performance analysis, inter-die transaction integrity verification, using a versatile SystemVerilog UVM-based environment. This integrated framework offers a scalable solution to the complex verification challenges presented by chiplet-based architectures, facilitating the development of more robust and efficient semiconductor designs in the post-Moore's Law landscape. We address current industry needs and anticipate future requirements in the evolving field of heterogeneous integration. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/dvconindia-2024ucie-241009173534-64edc362-thumbnail.jpg?width=120&height=120&fit=bounds" /> This presentation introduces a comprehensive verification methodology for Universal Chiplet Interconnect Express (UCIe) technology, addressing the intricate challenges inherent in multi-die system design. Our approach encompasses three critical domains: optimization of multi-die system verification, rigorous validation of automotive-grade UCIe IP, and enhancement of overall verification quality and efficiency. We demonstrate substantial improvements in verification throughput and silicon quality by employing advanced techniques such as in-depth performance analysis, inter-die transaction integrity verification, using a versatile SystemVerilog UVM-based environment. This integrated framework offers a scalable solution to the complex verification challenges presented by chiplet-based architectures, facilitating the development of more robust and efficient semiconductor designs in the post-Moore's Law landscape. We address current industry needs and anticipate future requirements in the evolving field of heterogeneous integration.

Universal Chip interconnect Verification from Pankaj Singh

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0 An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of High-Speed SerDes /slideshow/an-approach-to-overcome-modeling-inaccuracies-for-performance-simulation-signoff-of-highspeed-serdes/250983508 dvconindia2021rnmforperformance-220112132304
RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff. This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation. ]]>
RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff. This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation. ]]> Wed, 12 Jan 2022 13:23:03 GMT /slideshow/an-approach-to-overcome-modeling-inaccuracies-for-performance-simulation-signoff-of-highspeed-serdes/250983508 PankajSingh137@slideshare.net(PankajSingh137) An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of High-Speed SerDes PankajSingh137 RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff. This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/dvconindia2021rnmforperformance-220112132304-thumbnail.jpg?width=120&height=120&fit=bounds" /> RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff. This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation.

An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of High-Speed SerDes from Pankaj Singh

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0 Unified methodology for effective correlation of soc power /slideshow/unified-methodology-for-effective-correlation-of-soc-power/190657561 unifiedmethodologyforeffectivecorrelationofsocpowerv2-191105104453
Unified Framework across Pre and Post Silicon platforms for accurate power estimation and measurements ]]>
Unified Framework across Pre and Post Silicon platforms for accurate power estimation and measurements ]]> Tue, 05 Nov 2019 10:44:53 GMT /slideshow/unified-methodology-for-effective-correlation-of-soc-power/190657561 PankajSingh137@slideshare.net(PankajSingh137) Unified methodology for effective correlation of soc power PankajSingh137 Unified Framework across Pre and Post Silicon platforms for accurate power estimation and measurements <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/unifiedmethodologyforeffectivecorrelationofsocpowerv2-191105104453-thumbnail.jpg?width=120&height=120&fit=bounds" /> Unified Framework across Pre and Post Silicon platforms for accurate power estimation and measurements

Unified methodology for effective correlation of soc power from Pankaj Singh

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0 Overcoming challenges of_verifying complex mixed signal designs /PankajSingh137/overcoming-challenges-ofverifying-complex-mixed-signal-designs overcomingchallengesofverifyingcomplexmsdesigns-190830055244
Efficient and Innovative Digital Mixed-Signal (DMS) verification methodology is required to enable effective verification of RX path of SERDES. This presentation describes the usage of Real value models and Capture -Verify approach to verify complex high speed mixed signal design. Real value models are the backbone of DMS methodology. Real value models are created for all critical modules in Receive path like Equalizer and Sampler and its associated peripheral modules. It is critical to make sure created models are functionally equivalent to respective designs. This is achieved by verifying each created model with respective designs for all functional modes. While the Real Value models are effective in meeting overcoming the simulation performance bottleneck by achieving 10x faster simulation time; the Nonlinearity factors of the front-end design are not represented accurately in discrete domain real value models for next generation of SerDes Design at very high data rate. To overcome this problem, a novel approach called ‘capture and verify’ is used for verifying the jitter tolerance and eye parameters. In this approach, waveforms from spice level verification of Equalizer for different functional modes are captured and stored. These stored waveforms are used to generate run time table-based models to accurately represent the analog modules. These run time models are used in top-level simulations along with real value models thereby achieving required goal of simulation performance without compromising on accuracy of results. The complete Design Verification (DV) environment is developed using UVM-e Methodology. Verification environment contains model for transmitter with all de-emphasis settings along with protocol compliant channels with multiple attenuations. DV infrastructure has hooks to plug-in required channel models to verify SERDES. This verification environment is also capable of verifying the clock data recovery (CDR) path of the design using protocol compliant jitter and Spread-Spectrum Clocking (SSC) stimulus. The real value modelling bridges the gap between the performance requirements of the simulation and accuracy limitations of design. A significant speed-up in simulation performance is achieved (almost 10X in this case) by replacing with functionally equivalent real value models for mixed signal designs. Usage of Capture and Verify methodology with spice simulation waveforms for critical blocks ensures non-linearity of the next generation high speed SerDes design is well captured in simulations provide complete comprehensive solution for high speed mixed signal designs. ]]>
Efficient and Innovative Digital Mixed-Signal (DMS) verification methodology is required to enable effective verification of RX path of SERDES. This presentation describes the usage of Real value models and Capture -Verify approach to verify complex high speed mixed signal design. Real value models are the backbone of DMS methodology. Real value models are created for all critical modules in Receive path like Equalizer and Sampler and its associated peripheral modules. It is critical to make sure created models are functionally equivalent to respective designs. This is achieved by verifying each created model with respective designs for all functional modes. While the Real Value models are effective in meeting overcoming the simulation performance bottleneck by achieving 10x faster simulation time; the Nonlinearity factors of the front-end design are not represented accurately in discrete domain real value models for next generation of SerDes Design at very high data rate. To overcome this problem, a novel approach called ‘capture and verify’ is used for verifying the jitter tolerance and eye parameters. In this approach, waveforms from spice level verification of Equalizer for different functional modes are captured and stored. These stored waveforms are used to generate run time table-based models to accurately represent the analog modules. These run time models are used in top-level simulations along with real value models thereby achieving required goal of simulation performance without compromising on accuracy of results. The complete Design Verification (DV) environment is developed using UVM-e Methodology. Verification environment contains model for transmitter with all de-emphasis settings along with protocol compliant channels with multiple attenuations. DV infrastructure has hooks to plug-in required channel models to verify SERDES. This verification environment is also capable of verifying the clock data recovery (CDR) path of the design using protocol compliant jitter and Spread-Spectrum Clocking (SSC) stimulus. The real value modelling bridges the gap between the performance requirements of the simulation and accuracy limitations of design. A significant speed-up in simulation performance is achieved (almost 10X in this case) by replacing with functionally equivalent real value models for mixed signal designs. Usage of Capture and Verify methodology with spice simulation waveforms for critical blocks ensures non-linearity of the next generation high speed SerDes design is well captured in simulations provide complete comprehensive solution for high speed mixed signal designs. ]]> Fri, 30 Aug 2019 05:52:44 GMT /PankajSingh137/overcoming-challenges-ofverifying-complex-mixed-signal-designs PankajSingh137@slideshare.net(PankajSingh137) Overcoming challenges of_verifying complex mixed signal designs PankajSingh137 Efficient and Innovative Digital Mixed-Signal (DMS) verification methodology is required to enable effective verification of RX path of SERDES. This presentation describes the usage of Real value models and Capture -Verify approach to verify complex high speed mixed signal design. Real value models are the backbone of DMS methodology. Real value models are created for all critical modules in Receive path like Equalizer and Sampler and its associated peripheral modules. It is critical to make sure created models are functionally equivalent to respective designs. This is achieved by verifying each created model with respective designs for all functional modes. While the Real Value models are effective in meeting overcoming the simulation performance bottleneck by achieving 10x faster simulation time; the Nonlinearity factors of the front-end design are not represented accurately in discrete domain real value models for next generation of SerDes Design at very high data rate. To overcome this problem, a novel approach called ‘capture and verify’ is used for verifying the jitter tolerance and eye parameters. In this approach, waveforms from spice level verification of Equalizer for different functional modes are captured and stored. These stored waveforms are used to generate run time table-based models to accurately represent the analog modules. These run time models are used in top-level simulations along with real value models thereby achieving required goal of simulation performance without compromising on accuracy of results. The complete Design Verification (DV) environment is developed using UVM-e Methodology. Verification environment contains model for transmitter with all de-emphasis settings along with protocol compliant channels with multiple attenuations. DV infrastructure has hooks to plug-in required channel models to verify SERDES. This verification environment is also capable of verifying the clock data recovery (CDR) path of the design using protocol compliant jitter and Spread-Spectrum Clocking (SSC) stimulus. The real value modelling bridges the gap between the performance requirements of the simulation and accuracy limitations of design. A significant speed-up in simulation performance is achieved (almost 10X in this case) by replacing with functionally equivalent real value models for mixed signal designs. Usage of Capture and Verify methodology with spice simulation waveforms for critical blocks ensures non-linearity of the next generation high speed SerDes design is well captured in simulations provide complete comprehensive solution for high speed mixed signal designs. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/overcomingchallengesofverifyingcomplexmsdesigns-190830055244-thumbnail.jpg?width=120&height=120&fit=bounds" /> Efficient and Innovative Digital Mixed-Signal (DMS) verification methodology is required to enable effective verification of RX path of SERDES. This presentation describes the usage of Real value models and Capture -Verify approach to verify complex high speed mixed signal design. Real value models are the backbone of DMS methodology. Real value models are created for all critical modules in Receive path like Equalizer and Sampler and its associated peripheral modules. It is critical to make sure created models are functionally equivalent to respective designs. This is achieved by verifying each created model with respective designs for all functional modes. While the Real Value models are effective in meeting overcoming the simulation performance bottleneck by achieving 10x faster simulation time; the Nonlinearity factors of the front-end design are not represented accurately in discrete domain real value models for next generation of SerDes Design at very high data rate. To overcome this problem, a novel approach called ‘capture and verify’ is used for verifying the jitter tolerance and eye parameters. In this approach, waveforms from spice level verification of Equalizer for different functional modes are captured and stored. These stored waveforms are used to generate run time table-based models to accurately represent the analog modules. These run time models are used in top-level simulations along with real value models thereby achieving required goal of simulation performance without compromising on accuracy of results. The complete Design Verification (DV) environment is developed using UVM-e Methodology. Verification environment contains model for transmitter with all de-emphasis settings along with protocol compliant channels with multiple attenuations. DV infrastructure has hooks to plug-in required channel models to verify SERDES. This verification environment is also capable of verifying the clock data recovery (CDR) path of the design using protocol compliant jitter and Spread-Spectrum Clocking (SSC) stimulus. The real value modelling bridges the gap between the performance requirements of the simulation and accuracy limitations of design. A significant speed-up in simulation performance is achieved (almost 10X in this case) by replacing with functionally equivalent real value models for mixed signal designs. Usage of Capture and Verify methodology with spice simulation waveforms for critical blocks ensures non-linearity of the next generation high speed SerDes design is well captured in simulations provide complete comprehensive solution for high speed mixed signal designs.

Overcoming challenges of_verifying complex mixed signal designs from Pankaj Singh

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0 Qualifying a high performance memory subsysten for Functional Safety /slideshow/qualifying-a-high-performance-memory-subsysten-for-functional-safety/167651640 cadencequalifyingahighperformancememory-190830053640
Addressing the Challenges of Safety verification for LPDDR4. ✓Avoid traditional approach of starting functional safety after functional verification : Iterative and expensive development phase 1. Functional Safety Need to be Architected and not added later. 2. Safety Analysis must start prior to implementation. ‘Design for safety/verification’ 3. Reuse & Synergize : Nominal and Functional Safety Verification. ✓Fault optimization with formal and other techniques is necessary to overcome challenges with scaling simulation and analysis. ✓Integrated push button fault simulation flow is need of hour and saves verification engineers time. ✓Analog defect modelling and coverage can be performed based on IEEE P2427. ]]>
Addressing the Challenges of Safety verification for LPDDR4. ✓Avoid traditional approach of starting functional safety after functional verification : Iterative and expensive development phase 1. Functional Safety Need to be Architected and not added later. 2. Safety Analysis must start prior to implementation. ‘Design for safety/verification’ 3. Reuse & Synergize : Nominal and Functional Safety Verification. ✓Fault optimization with formal and other techniques is necessary to overcome challenges with scaling simulation and analysis. ✓Integrated push button fault simulation flow is need of hour and saves verification engineers time. ✓Analog defect modelling and coverage can be performed based on IEEE P2427. ]]> Fri, 30 Aug 2019 05:36:40 GMT /slideshow/qualifying-a-high-performance-memory-subsysten-for-functional-safety/167651640 PankajSingh137@slideshare.net(PankajSingh137) Qualifying a high performance memory subsysten for Functional Safety PankajSingh137 Addressing the Challenges of Safety verification for LPDDR4. ✓Avoid traditional approach of starting functional safety after functional verification : Iterative and expensive development phase 1. Functional Safety Need to be Architected and not added later. 2. Safety Analysis must start prior to implementation. ‘Design for safety/verification’ 3. Reuse & Synergize : Nominal and Functional Safety Verification. ✓Fault optimization with formal and other techniques is necessary to overcome challenges with scaling simulation and analysis. ✓Integrated push button fault simulation flow is need of hour and saves verification engineers time. ✓Analog defect modelling and coverage can be performed based on IEEE P2427. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/cadencequalifyingahighperformancememory-190830053640-thumbnail.jpg?width=120&height=120&fit=bounds" /> Addressing the Challenges of Safety verification for LPDDR4. ✓Avoid traditional approach of starting functional safety after functional verification : Iterative and expensive development phase 1. Functional Safety Need to be Architected and not added later. 2. Safety Analysis must start prior to implementation. ‘Design for safety/verification’ 3. Reuse & Synergize : Nominal and Functional Safety Verification. ✓Fault optimization with formal and other techniques is necessary to overcome challenges with scaling simulation and analysis. ✓Integrated push button fault simulation flow is need of hour and saves verification engineers time. ✓Analog defect modelling and coverage can be performed based on IEEE P2427.

Qualifying a high performance memory subsysten for Functional Safety from Pankaj Singh

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0 Safety Verification and Software aspects of Automotive SoC /slideshow/safety-verification-and-software-aspects-of-automotive-soc/84513246 ipsoc2017grenobleinifneonpankajsingh-171220055818
IP-SoC Conference 2017 Grenoble Automotive industry has evolved over last 100 years. Electronic systems were introduced into the automotive industry in 1960. Since then the complexity has grown many fold and today’s automobiles have as many as 150 programmable computing elements or Electronic Control Units(ECUs) with several wiring connections. The software content has also increased significantly with today’s car having more than 100 million of lines of software code. This increased hardware and software complexity increases the risk of failure that could impact negatively on vehicle safety. This has led to concerns regarding the validation of failure modes and the detection mechanisms. Car maker and suppliers need to prove that, despite increasing complexity, their electronic systems will deliver the required functionality safely and reliably. This presentation describes the challenges and methodology related to Safety verification and Software development aspects of Automotive Microcontroller SoC. ]]>
IP-SoC Conference 2017 Grenoble Automotive industry has evolved over last 100 years. Electronic systems were introduced into the automotive industry in 1960. Since then the complexity has grown many fold and today’s automobiles have as many as 150 programmable computing elements or Electronic Control Units(ECUs) with several wiring connections. The software content has also increased significantly with today’s car having more than 100 million of lines of software code. This increased hardware and software complexity increases the risk of failure that could impact negatively on vehicle safety. This has led to concerns regarding the validation of failure modes and the detection mechanisms. Car maker and suppliers need to prove that, despite increasing complexity, their electronic systems will deliver the required functionality safely and reliably. This presentation describes the challenges and methodology related to Safety verification and Software development aspects of Automotive Microcontroller SoC. ]]> Wed, 20 Dec 2017 05:58:17 GMT /slideshow/safety-verification-and-software-aspects-of-automotive-soc/84513246 PankajSingh137@slideshare.net(PankajSingh137) Safety Verification and Software aspects of Automotive SoC PankajSingh137 IP-SoC Conference 2017 Grenoble Automotive industry has evolved over last 100 years. Electronic systems were introduced into the automotive industry in 1960. Since then the complexity has grown many fold and today’s automobiles have as many as 150 programmable computing elements or Electronic Control Units(ECUs) with several wiring connections. The software content has also increased significantly with today’s car having more than 100 million of lines of software code. This increased hardware and software complexity increases the risk of failure that could impact negatively on vehicle safety. This has led to concerns regarding the validation of failure modes and the detection mechanisms. Car maker and suppliers need to prove that, despite increasing complexity, their electronic systems will deliver the required functionality safely and reliably. This presentation describes the challenges and methodology related to Safety verification and Software development aspects of Automotive Microcontroller SoC. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/ipsoc2017grenobleinifneonpankajsingh-171220055818-thumbnail.jpg?width=120&height=120&fit=bounds" /> IP-SoC Conference 2017 Grenoble Automotive industry has evolved over last 100 years. Electronic systems were introduced into the automotive industry in 1960. Since then the complexity has grown many fold and today’s automobiles have as many as 150 programmable computing elements or Electronic Control Units(ECUs) with several wiring connections. The software content has also increased significantly with today’s car having more than 100 million of lines of software code. This increased hardware and software complexity increases the risk of failure that could impact negatively on vehicle safety. This has led to concerns regarding the validation of failure modes and the detection mechanisms. Car maker and suppliers need to prove that, despite increasing complexity, their electronic systems will deliver the required functionality safely and reliably. This presentation describes the challenges and methodology related to Safety verification and Software development aspects of Automotive Microcontroller SoC.

Safety Verification and Software aspects of Automotive SoC from Pankaj Singh

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0 Thesis /slideshow/thesis-65820234/65820234 thesis-160908115408
Most efficient Fast Hartley Transform Algorithm (FHT) (available at the time of publication).]]>
Most efficient Fast Hartley Transform Algorithm (FHT) (available at the time of publication).]]> Thu, 08 Sep 2016 11:54:08 GMT /slideshow/thesis-65820234/65820234 PankajSingh137@slideshare.net(PankajSingh137) Thesis PankajSingh137 Most efficient Fast Hartley Transform Algorithm (FHT) (available at the time of publication). <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/thesis-160908115408-thumbnail.jpg?width=120&height=120&fit=bounds" /> Most efficient Fast Hartley Transform Algorithm (FHT) (available at the time of publication).

Thesis from Pankaj Singh

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0 Managing securityforautomotivesoc /slideshow/managing-securityforautomotivesoc/60992378 managingsecurityforautomotivesoc-160416151236
1.Car Security Understanding the Car Onboard Communication / Connection and inherent Security Weakness 2.Addressing the Security Concerns : System’s Viewpoint Hardware Security Module & Secure Hardware Extension Look at Software Principle of MAC and Associated Hardware 3.Achieving Security implementation checks via Software and Addressing the Hardware Safety aspect. Closing the Loop for Security Safeness: Complete Solution to Ensure Security/Safety Compliance with Software ]]>
1.Car Security Understanding the Car Onboard Communication / Connection and inherent Security Weakness 2.Addressing the Security Concerns : System’s Viewpoint Hardware Security Module & Secure Hardware Extension Look at Software Principle of MAC and Associated Hardware 3.Achieving Security implementation checks via Software and Addressing the Hardware Safety aspect. Closing the Loop for Security Safeness: Complete Solution to Ensure Security/Safety Compliance with Software ]]> Sat, 16 Apr 2016 15:12:36 GMT /slideshow/managing-securityforautomotivesoc/60992378 PankajSingh137@slideshare.net(PankajSingh137) Managing securityforautomotivesoc PankajSingh137 1.Car Security Understanding the Car Onboard Communication / Connection and inherent Security Weakness 2.Addressing the Security Concerns : System’s Viewpoint Hardware Security Module & Secure Hardware Extension Look at Software Principle of MAC and Associated Hardware 3.Achieving Security implementation checks via Software and Addressing the Hardware Safety aspect. Closing the Loop for Security Safeness: Complete Solution to Ensure Security/Safety Compliance with Software <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/managingsecurityforautomotivesoc-160416151236-thumbnail.jpg?width=120&height=120&fit=bounds" /> 1.Car Security Understanding the Car Onboard Communication / Connection and inherent Security Weakness 2.Addressing the Security Concerns : System’s Viewpoint Hardware Security Module & Secure Hardware Extension Look at Software Principle of MAC and Associated Hardware 3.Achieving Security implementation checks via Software and Addressing the Hardware Safety aspect. Closing the Loop for Security Safeness: Complete Solution to Ensure Security/Safety Compliance with Software

Managing securityforautomotivesoc from Pankaj Singh

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0 Panel:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software /slideshow/panelthe-secret-of-indian-leadership-in-electronic-design-skill-from-design-to-services-to-embedded-software/60070360 dripconference2015bangalorepankajsingh-160327032825
Panel Discussion: D&R IP-SoC, Bangalore 2015. Topic:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software]]>
Panel Discussion: D&R IP-SoC, Bangalore 2015. Topic:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software]]> Sun, 27 Mar 2016 03:28:25 GMT /slideshow/panelthe-secret-of-indian-leadership-in-electronic-design-skill-from-design-to-services-to-embedded-software/60070360 PankajSingh137@slideshare.net(PankajSingh137) Panel:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software PankajSingh137 Panel Discussion: D&R IP-SoC, Bangalore 2015. Topic:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/dripconference2015bangalorepankajsingh-160327032825-thumbnail.jpg?width=120&height=120&fit=bounds" /> Panel Discussion: D&R IP-SoC, Bangalore 2015. Topic:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software

Panel:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software from Pankaj Singh

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0 OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY /slideshow/overcoming-key-challenges-of-todays-complex-soc-performance-optimization-and-verification-quality/40971230 perfoptimizationsocverification-141031114315-conversion-gate02
EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS SKIN TEMPERATURE AWARE POWER MANAGEMENT AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT] DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT HOLISTIC VIEW OF SOC VERIFICATION : EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT. EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION. H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN.]]>
EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS SKIN TEMPERATURE AWARE POWER MANAGEMENT AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT] DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT HOLISTIC VIEW OF SOC VERIFICATION : EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT. EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION. H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN.]]> Fri, 31 Oct 2014 11:43:15 GMT /slideshow/overcoming-key-challenges-of-todays-complex-soc-performance-optimization-and-verification-quality/40971230 PankajSingh137@slideshare.net(PankajSingh137) OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY PankajSingh137 EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS SKIN TEMPERATURE AWARE POWER MANAGEMENT AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT] DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT HOLISTIC VIEW OF SOC VERIFICATION : EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT. EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION. H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/perfoptimizationsocverification-141031114315-conversion-gate02-thumbnail.jpg?width=120&height=120&fit=bounds" /> EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS SKIN TEMPERATURE AWARE POWER MANAGEMENT AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT] DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT HOLISTIC VIEW OF SOC VERIFICATION : EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT. EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION. H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN.

OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY from Pankaj Singh

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0 AMD_11th_Intl_SoC_Conf_UCI_Irvine /slideshow/amd-11thintlsocconfuci/27875263 amd11thintlsocconfuci-131103224721-phpapp01
1] A New Parallel Computing Platform – Heterogeneous System Architecture Opportunities, Benefits and Feature Roadmap 2] Kaveri Platform Coherency Shared memory, Platform atomics 3] Kaveri Verification Approach 4] SoC Verification Challenges and Solutions]]>
1] A New Parallel Computing Platform – Heterogeneous System Architecture Opportunities, Benefits and Feature Roadmap 2] Kaveri Platform Coherency Shared memory, Platform atomics 3] Kaveri Verification Approach 4] SoC Verification Challenges and Solutions]]> Sun, 03 Nov 2013 22:47:21 GMT /slideshow/amd-11thintlsocconfuci/27875263 PankajSingh137@slideshare.net(PankajSingh137) AMD_11th_Intl_SoC_Conf_UCI_Irvine PankajSingh137 1] A New Parallel Computing Platform – Heterogeneous System Architecture Opportunities, Benefits and Feature Roadmap 2] Kaveri Platform Coherency Shared memory, Platform atomics 3] Kaveri Verification Approach 4] SoC Verification Challenges and Solutions <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/amd11thintlsocconfuci-131103224721-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /> 1] A New Parallel Computing Platform – Heterogeneous System Architecture Opportunities, Benefits and Feature Roadmap 2] Kaveri Platform Coherency Shared memory, Platform atomics 3] Kaveri Verification Approach 4] SoC Verification Challenges and Solutions

AMD_11th_Intl_SoC_Conf_UCI_Irvine from Pankaj Singh

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0 Power Optimization with Efficient Test Logic Partitioning for Full Chip Design /slideshow/test-power-reduction/25059861 testpowerreduction-130808090407-phpapp01
This paper introduces efficient test logic partitioning to not only optimize and reduce the overall test power during silicon validation but also reduce power in functional mode by shutting off test logic. Approach used in optimizing test power has been successful in reducing overall functional mode leakage power by 50% without any additional area overhead or test time increase. Results shared are based on WIMAX full chip SoC design.]]>
This paper introduces efficient test logic partitioning to not only optimize and reduce the overall test power during silicon validation but also reduce power in functional mode by shutting off test logic. Approach used in optimizing test power has been successful in reducing overall functional mode leakage power by 50% without any additional area overhead or test time increase. Results shared are based on WIMAX full chip SoC design.]]> Thu, 08 Aug 2013 09:04:07 GMT /slideshow/test-power-reduction/25059861 PankajSingh137@slideshare.net(PankajSingh137) Power Optimization with Efficient Test Logic Partitioning for Full Chip Design PankajSingh137 This paper introduces efficient test logic partitioning to not only optimize and reduce the overall test power during silicon validation but also reduce power in functional mode by shutting off test logic. Approach used in optimizing test power has been successful in reducing overall functional mode leakage power by 50% without any additional area overhead or test time increase. Results shared are based on WIMAX full chip SoC design. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/testpowerreduction-130808090407-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /> This paper introduces efficient test logic partitioning to not only optimize and reduce the overall test power during silicon validation but also reduce power in functional mode by shutting off test logic. Approach used in optimizing test power has been successful in reducing overall functional mode leakage power by 50% without any additional area overhead or test time increase. Results shared are based on WIMAX full chip SoC design.

Power Optimization with Efficient Test Logic Partitioning for Full Chip Design from Pankaj Singh

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0 FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN /slideshow/amd-9th-intlsocconf-presentation/24211164 amd9thintlsocconf-130713202956-phpapp01
9th International SoC Conference 2011 FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN]]>
9th International SoC Conference 2011 FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN]]> Sat, 13 Jul 2013 20:29:56 GMT /slideshow/amd-9th-intlsocconf-presentation/24211164 PankajSingh137@slideshare.net(PankajSingh137) FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN PankajSingh137 9th International SoC Conference 2011 FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/amd9thintlsocconf-130713202956-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /> 9th International SoC Conference 2011 FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN

FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN from Pankaj Singh

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0 https://cdn.slidesharecdn.com/profile-photo-PankajSingh137-48x48.jpg?cb=1729705811 MBA, Southern Methodist University.SMU Dallas,Texas,99-01 M.S.E.E, University of South Florida. Tampa, Florida. 95-97 B.E. in electronics, REC(NIT). Bhopal University, India.89-93 IP , full chip SoC design, project/program mgmt, Design flow (R2G,functional+system verification, software infrastr.), lead global cross site SoC verification teams. Specialties: Seasoned semiconductor professional; 19 years of industry experience with startups and large US,European MNC's. Management experience includes building team from scratch, motivating and managing multiple teams/project mgr to excel and meet customer expectations; Managing customer interface/program mgmt of complex SoC’s,IP development.. https://cdn.slidesharecdn.com/ss_thumbnails/dvconindia-2024ucie-241009173534-64edc362-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/universal-chip-interconnect-verification/272299647 Universal Chip interco... https://cdn.slidesharecdn.com/ss_thumbnails/dvconindia2021rnmforperformance-220112132304-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/an-approach-to-overcome-modeling-inaccuracies-for-performance-simulation-signoff-of-highspeed-serdes/250983508 An Approach to Overcom... https://cdn.slidesharecdn.com/ss_thumbnails/unifiedmethodologyforeffectivecorrelationofsocpowerv2-191105104453-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/unified-methodology-for-effective-correlation-of-soc-power/190657561 Unified methodology fo...