ºÝºÝߣshows by User: prasenjitdey15 / http://www.slideshare.net/images/logo.gif ºÝºÝߣshows by User: prasenjitdey15 / Sun, 11 Jul 2021 20:09:06 GMT ºÝºÝߣShare feed for ºÝºÝߣshows by User: prasenjitdey15 Dynamic interconnection networks /slideshow/dynamic-interconnection-network/249688151 dynamicinterconnectionnetwork-210711200907
Discussed different types of dynamic interconnection networks. Graphically demonstrated single and multiple bus interconnection networks. Discussed different types of switch based interconnection networks. Graphically shown the mechanisms of crossbar, single and multistage interconnection networks. Graphically explained the working principle of omega network, Benes network, and baseline networks.]]>

Discussed different types of dynamic interconnection networks. Graphically demonstrated single and multiple bus interconnection networks. Discussed different types of switch based interconnection networks. Graphically shown the mechanisms of crossbar, single and multistage interconnection networks. Graphically explained the working principle of omega network, Benes network, and baseline networks.]]>
Sun, 11 Jul 2021 20:09:06 GMT /slideshow/dynamic-interconnection-network/249688151 prasenjitdey15@slideshare.net(prasenjitdey15) Dynamic interconnection networks prasenjitdey15 Discussed different types of dynamic interconnection networks. Graphically demonstrated single and multiple bus interconnection networks. Discussed different types of switch based interconnection networks. Graphically shown the mechanisms of crossbar, single and multistage interconnection networks. Graphically explained the working principle of omega network, Benes network, and baseline networks. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/dynamicinterconnectionnetwork-210711200907-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Discussed different types of dynamic interconnection networks. Graphically demonstrated single and multiple bus interconnection networks. Discussed different types of switch based interconnection networks. Graphically shown the mechanisms of crossbar, single and multistage interconnection networks. Graphically explained the working principle of omega network, Benes network, and baseline networks.
Dynamic interconnection networks from Prasenjit Dey
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Machine Learning in Agriculture Module 6: classification /prasenjitdey15/machine-lllearning-in-agriculture-module-6-classification machinelearninginagriculturemodule6classification-210709203000
Define the classification problem. Discuss different performance evaluation metrics in classification problem, Graphically demonstrate the concepts of true positive, true negative, false positive, false negative, sensitivity and specificity, confusion matrix, precision and recall, Concepts of ROC and AUC curve ]]>

Define the classification problem. Discuss different performance evaluation metrics in classification problem, Graphically demonstrate the concepts of true positive, true negative, false positive, false negative, sensitivity and specificity, confusion matrix, precision and recall, Concepts of ROC and AUC curve ]]>
Fri, 09 Jul 2021 20:29:59 GMT /prasenjitdey15/machine-lllearning-in-agriculture-module-6-classification prasenjitdey15@slideshare.net(prasenjitdey15) Machine Learning in Agriculture Module 6: classification prasenjitdey15 Define the classification problem. Discuss different performance evaluation metrics in classification problem, Graphically demonstrate the concepts of true positive, true negative, false positive, false negative, sensitivity and specificity, confusion matrix, precision and recall, Concepts of ROC and AUC curve <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/machinelearninginagriculturemodule6classification-210709203000-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Define the classification problem. Discuss different performance evaluation metrics in classification problem, Graphically demonstrate the concepts of true positive, true negative, false positive, false negative, sensitivity and specificity, confusion matrix, precision and recall, Concepts of ROC and AUC curve
Machine Learning in Agriculture Module 6: classification from Prasenjit Dey
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Machine Learning in Agriculture Module 3: linear regression /slideshow/machine-learning-in-agriculture-module-3-linear-regression/249673743 machinelearninginagriculturemodule3linearregression-210709201207
Crop yield prediction from a tiny data set by using linear regression model in python]]>

Crop yield prediction from a tiny data set by using linear regression model in python]]>
Fri, 09 Jul 2021 20:12:06 GMT /slideshow/machine-learning-in-agriculture-module-3-linear-regression/249673743 prasenjitdey15@slideshare.net(prasenjitdey15) Machine Learning in Agriculture Module 3: linear regression prasenjitdey15 Crop yield prediction from a tiny data set by using linear regression model in python <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/machinelearninginagriculturemodule3linearregression-210709201207-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Crop yield prediction from a tiny data set by using linear regression model in python
Machine Learning in Agriculture Module 3: linear regression from Prasenjit Dey
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Machine learning in agriculture module 2 /slideshow/machine-learning-in-agriculture-module-2-249673737/249673737 machinelearninginagriculturemodule2-210709200647
Discussed basic concepts of machine learning, different learning algorithms of machine learning, e.g., supervised learning, unsupervised learning, reinforced learning. Discussed different types of problems solved by machine learning, e.g., classification problems, clustering, regression problems• Regression analysis ]]>

Discussed basic concepts of machine learning, different learning algorithms of machine learning, e.g., supervised learning, unsupervised learning, reinforced learning. Discussed different types of problems solved by machine learning, e.g., classification problems, clustering, regression problems• Regression analysis ]]>
Fri, 09 Jul 2021 20:06:46 GMT /slideshow/machine-learning-in-agriculture-module-2-249673737/249673737 prasenjitdey15@slideshare.net(prasenjitdey15) Machine learning in agriculture module 2 prasenjitdey15 Discussed basic concepts of machine learning, different learning algorithms of machine learning, e.g., supervised learning, unsupervised learning, reinforced learning. Discussed different types of problems solved by machine learning, e.g., classification problems, clustering, regression problems• Regression analysis <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/machinelearninginagriculturemodule2-210709200647-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Discussed basic concepts of machine learning, different learning algorithms of machine learning, e.g., supervised learning, unsupervised learning, reinforced learning. Discussed different types of problems solved by machine learning, e.g., classification problems, clustering, regression problems• Regression analysis
Machine learning in agriculture module 2 from Prasenjit Dey
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Machine Learning in Agriculture Module 1 /slideshow/machine-learning-in-agriculture-module-1-249673720/249673720 machinelearninginagriculturemodule1-210709195507
Discuss the opportunities of incorporation of machine learning in agriculture. Briefly discuss different machine learning strategies. Briefly discuss the ways of machine learning can be used]]>

Discuss the opportunities of incorporation of machine learning in agriculture. Briefly discuss different machine learning strategies. Briefly discuss the ways of machine learning can be used]]>
Fri, 09 Jul 2021 19:55:06 GMT /slideshow/machine-learning-in-agriculture-module-1-249673720/249673720 prasenjitdey15@slideshare.net(prasenjitdey15) Machine Learning in Agriculture Module 1 prasenjitdey15 Discuss the opportunities of incorporation of machine learning in agriculture. Briefly discuss different machine learning strategies. Briefly discuss the ways of machine learning can be used <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/machinelearninginagriculturemodule1-210709195507-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Discuss the opportunities of incorporation of machine learning in agriculture. Briefly discuss different machine learning strategies. Briefly discuss the ways of machine learning can be used
Machine Learning in Agriculture Module 1 from Prasenjit Dey
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Support vector machine /slideshow/support-vector-machine-249594781/249594781 supportvectormachine-210704195413
Explained the concepts behind Support Vector Machine (SVM)]]>

Explained the concepts behind Support Vector Machine (SVM)]]>
Sun, 04 Jul 2021 19:54:12 GMT /slideshow/support-vector-machine-249594781/249594781 prasenjitdey15@slideshare.net(prasenjitdey15) Support vector machine prasenjitdey15 Explained the concepts behind Support Vector Machine (SVM) <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/supportvectormachine-210704195413-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Explained the concepts behind Support Vector Machine (SVM)
Support vector machine from Prasenjit Dey
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Numerical on general pipelines /slideshow/numerical-on-general-pipelines/249516204 numericalongeneralpipelines-210628103104
Numerical on general pipelines, computation of reservation table, state diagram, simple cycle, greedy cycle, minimum, average latency]]>

Numerical on general pipelines, computation of reservation table, state diagram, simple cycle, greedy cycle, minimum, average latency]]>
Mon, 28 Jun 2021 10:31:04 GMT /slideshow/numerical-on-general-pipelines/249516204 prasenjitdey15@slideshare.net(prasenjitdey15) Numerical on general pipelines prasenjitdey15 Numerical on general pipelines, computation of reservation table, state diagram, simple cycle, greedy cycle, minimum, average latency <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/numericalongeneralpipelines-210628103104-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Numerical on general pipelines, computation of reservation table, state diagram, simple cycle, greedy cycle, minimum, average latency
Numerical on general pipelines from Prasenjit Dey
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General pipeline concepts /slideshow/general-pipeline-concepts/249515066 generalpipelineconcepts-210628085949
Describe the non linear dynamic pipeline concepts, Creation of reservation table from non-linear pipeline architecture, creation of collision vector from reservation table, generation of state diagram, derivation of simple cycles, greedy cycles and MAL(Minimum Average Latency)]]>

Describe the non linear dynamic pipeline concepts, Creation of reservation table from non-linear pipeline architecture, creation of collision vector from reservation table, generation of state diagram, derivation of simple cycles, greedy cycles and MAL(Minimum Average Latency)]]>
Mon, 28 Jun 2021 08:59:49 GMT /slideshow/general-pipeline-concepts/249515066 prasenjitdey15@slideshare.net(prasenjitdey15) General pipeline concepts prasenjitdey15 Describe the non linear dynamic pipeline concepts, Creation of reservation table from non-linear pipeline architecture, creation of collision vector from reservation table, generation of state diagram, derivation of simple cycles, greedy cycles and MAL(Minimum Average Latency) <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/generalpipelineconcepts-210628085949-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Describe the non linear dynamic pipeline concepts, Creation of reservation table from non-linear pipeline architecture, creation of collision vector from reservation table, generation of state diagram, derivation of simple cycles, greedy cycles and MAL(Minimum Average Latency)
General pipeline concepts from Prasenjit Dey
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Evaluation of computer performance /slideshow/evaluation-of-computer-performance/249398192 evaluationofcomputerperformance-210617163445
Explained response time and CPU time, difference between them, Explained clock cycle time, clock frequency, clock rate, cycle per instruction(CPI), million instruction per second(MIPS), etc. Describe Amdahl's law with numerical examples]]>

Explained response time and CPU time, difference between them, Explained clock cycle time, clock frequency, clock rate, cycle per instruction(CPI), million instruction per second(MIPS), etc. Describe Amdahl's law with numerical examples]]>
Thu, 17 Jun 2021 16:34:44 GMT /slideshow/evaluation-of-computer-performance/249398192 prasenjitdey15@slideshare.net(prasenjitdey15) Evaluation of computer performance prasenjitdey15 Explained response time and CPU time, difference between them, Explained clock cycle time, clock frequency, clock rate, cycle per instruction(CPI), million instruction per second(MIPS), etc. Describe Amdahl's law with numerical examples <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/evaluationofcomputerperformance-210617163445-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Explained response time and CPU time, difference between them, Explained clock cycle time, clock frequency, clock rate, cycle per instruction(CPI), million instruction per second(MIPS), etc. Describe Amdahl&#39;s law with numerical examples
Evaluation of computer performance from Prasenjit Dey
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Instruction Set Architecture: MIPS /slideshow/instruction-set-architecture-mips/248796925 instructionsetarchitecturemips-210531172400
Defined instruction set architecture, discussed different types of instructions in the MIPS architecture, e.g., arithmetic, logical, shift etc. Discussed different types of registers in MIPS, R-format, I-format and j-format instructions have been explained with examples. Further assembly language code for conditional operations e.g., if..else, swap operation, loop operation are demonstrated. ]]>

Defined instruction set architecture, discussed different types of instructions in the MIPS architecture, e.g., arithmetic, logical, shift etc. Discussed different types of registers in MIPS, R-format, I-format and j-format instructions have been explained with examples. Further assembly language code for conditional operations e.g., if..else, swap operation, loop operation are demonstrated. ]]>
Mon, 31 May 2021 17:23:59 GMT /slideshow/instruction-set-architecture-mips/248796925 prasenjitdey15@slideshare.net(prasenjitdey15) Instruction Set Architecture: MIPS prasenjitdey15 Defined instruction set architecture, discussed different types of instructions in the MIPS architecture, e.g., arithmetic, logical, shift etc. Discussed different types of registers in MIPS, R-format, I-format and j-format instructions have been explained with examples. Further assembly language code for conditional operations e.g., if..else, swap operation, loop operation are demonstrated. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/instructionsetarchitecturemips-210531172400-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Defined instruction set architecture, discussed different types of instructions in the MIPS architecture, e.g., arithmetic, logical, shift etc. Discussed different types of registers in MIPS, R-format, I-format and j-format instructions have been explained with examples. Further assembly language code for conditional operations e.g., if..else, swap operation, loop operation are demonstrated.
Instruction Set Architecture: MIPS from Prasenjit Dey
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Page replacement and thrashing /prasenjitdey15/page-replacement-and-thrashing pagereplacementandthrashing-210303205340
Discussed different page replacement algorithms and their hardware implementation. Explained the cause of thrashing.]]>

Discussed different page replacement algorithms and their hardware implementation. Explained the cause of thrashing.]]>
Wed, 03 Mar 2021 20:53:39 GMT /prasenjitdey15/page-replacement-and-thrashing prasenjitdey15@slideshare.net(prasenjitdey15) Page replacement and thrashing prasenjitdey15 Discussed different page replacement algorithms and their hardware implementation. Explained the cause of thrashing. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/pagereplacementandthrashing-210303205340-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Discussed different page replacement algorithms and their hardware implementation. Explained the cause of thrashing.
Page replacement and thrashing from Prasenjit Dey
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Addressing mode /slideshow/addressing-mode-243570096/243570096 addressingmode-210227142414
Different types of addressing modes have been discussed]]>

Different types of addressing modes have been discussed]]>
Sat, 27 Feb 2021 14:24:13 GMT /slideshow/addressing-mode-243570096/243570096 prasenjitdey15@slideshare.net(prasenjitdey15) Addressing mode prasenjitdey15 Different types of addressing modes have been discussed <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/addressingmode-210227142414-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Different types of addressing modes have been discussed
Addressing mode from Prasenjit Dey
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Register transfer and microoperations part 2 /slideshow/register-transfer-and-microoperations-part-2/243569325 registertransferandmicrooperationspart2-210227141246
Discussed different types of micro-operations, e.g., arithmetic, logical, shift micro-operations. Explained Half Adder, Full Adder, Binary Adder subtractor. Discussed different types of logical micro-operations including XOR, OR, AND, NOT as well as Bit manipulation operations including, selective set, selective complement, insertion, reset, set etc. Discussed different types of shift micro-operations, arithmetic, logical, and circular shifts. Hardware implementation of a single unit (ALU) capable of performing all the arithmetic, logical and shift micro-operations.]]>

Discussed different types of micro-operations, e.g., arithmetic, logical, shift micro-operations. Explained Half Adder, Full Adder, Binary Adder subtractor. Discussed different types of logical micro-operations including XOR, OR, AND, NOT as well as Bit manipulation operations including, selective set, selective complement, insertion, reset, set etc. Discussed different types of shift micro-operations, arithmetic, logical, and circular shifts. Hardware implementation of a single unit (ALU) capable of performing all the arithmetic, logical and shift micro-operations.]]>
Sat, 27 Feb 2021 14:12:46 GMT /slideshow/register-transfer-and-microoperations-part-2/243569325 prasenjitdey15@slideshare.net(prasenjitdey15) Register transfer and microoperations part 2 prasenjitdey15 Discussed different types of micro-operations, e.g., arithmetic, logical, shift micro-operations. Explained Half Adder, Full Adder, Binary Adder subtractor. Discussed different types of logical micro-operations including XOR, OR, AND, NOT as well as Bit manipulation operations including, selective set, selective complement, insertion, reset, set etc. Discussed different types of shift micro-operations, arithmetic, logical, and circular shifts. Hardware implementation of a single unit (ALU) capable of performing all the arithmetic, logical and shift micro-operations. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/registertransferandmicrooperationspart2-210227141246-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Discussed different types of micro-operations, e.g., arithmetic, logical, shift micro-operations. Explained Half Adder, Full Adder, Binary Adder subtractor. Discussed different types of logical micro-operations including XOR, OR, AND, NOT as well as Bit manipulation operations including, selective set, selective complement, insertion, reset, set etc. Discussed different types of shift micro-operations, arithmetic, logical, and circular shifts. Hardware implementation of a single unit (ALU) capable of performing all the arithmetic, logical and shift micro-operations.
Register transfer and microoperations part 2 from Prasenjit Dey
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Instruction set (prasenjit dey) /slideshow/instruction-set-prasenjit-dey/242480943 instructionsetprasenjitdey-210209170748
Instruction Set, Instruction Format, Instruction Encoding, Instruction Cycle, Types of the instructions, Types of Operand, Instruction Length, Number of Addresses in an instruction]]>

Instruction Set, Instruction Format, Instruction Encoding, Instruction Cycle, Types of the instructions, Types of Operand, Instruction Length, Number of Addresses in an instruction]]>
Tue, 09 Feb 2021 17:07:47 GMT /slideshow/instruction-set-prasenjit-dey/242480943 prasenjitdey15@slideshare.net(prasenjitdey15) Instruction set (prasenjit dey) prasenjitdey15 Instruction Set, Instruction Format, Instruction Encoding, Instruction Cycle, Types of the instructions, Types of Operand, Instruction Length, Number of Addresses in an instruction <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/instructionsetprasenjitdey-210209170748-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Instruction Set, Instruction Format, Instruction Encoding, Instruction Cycle, Types of the instructions, Types of Operand, Instruction Length, Number of Addresses in an instruction
Instruction set (prasenjit dey) from Prasenjit Dey
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Register transfer and microoperations part 1 /slideshow/register-transfer-and-microoperations-part-1/241198998 registertransferandmicrooperationspart1-210111172535
Register transfer language, hardware implementation of bus transfer using multiplexer and three state buffer, hardware implementation of memory transfer e.g., memory read and memory write.]]>

Register transfer language, hardware implementation of bus transfer using multiplexer and three state buffer, hardware implementation of memory transfer e.g., memory read and memory write.]]>
Mon, 11 Jan 2021 17:25:35 GMT /slideshow/register-transfer-and-microoperations-part-1/241198998 prasenjitdey15@slideshare.net(prasenjitdey15) Register transfer and microoperations part 1 prasenjitdey15 Register transfer language, hardware implementation of bus transfer using multiplexer and three state buffer, hardware implementation of memory transfer e.g., memory read and memory write. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/registertransferandmicrooperationspart1-210111172535-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Register transfer language, hardware implementation of bus transfer using multiplexer and three state buffer, hardware implementation of memory transfer e.g., memory read and memory write.
Register transfer and microoperations part 1 from Prasenjit Dey
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Different types of memory and hardware designs of RAM and ROM /slideshow/different-types-of-memory-and-hardware-designs-of-ram-and-rom-241198974/241198974 differenttypesofmemoryandhardwaredesignsoframandrom-210111172259
Discussed the memory hierarchy, the characteristics of memory like location, unit of data transfer, access method, and performance. Then demonstrate the design of both RAM and ROM chip. Shows how to configure the memory unit composed of both RAM and ROM using multiple RAM and ROM chips i n hardware. Finally, demonstrate the design of the magnetic disks]]>

Discussed the memory hierarchy, the characteristics of memory like location, unit of data transfer, access method, and performance. Then demonstrate the design of both RAM and ROM chip. Shows how to configure the memory unit composed of both RAM and ROM using multiple RAM and ROM chips i n hardware. Finally, demonstrate the design of the magnetic disks]]>
Mon, 11 Jan 2021 17:22:58 GMT /slideshow/different-types-of-memory-and-hardware-designs-of-ram-and-rom-241198974/241198974 prasenjitdey15@slideshare.net(prasenjitdey15) Different types of memory and hardware designs of RAM and ROM prasenjitdey15 Discussed the memory hierarchy, the characteristics of memory like location, unit of data transfer, access method, and performance. Then demonstrate the design of both RAM and ROM chip. Shows how to configure the memory unit composed of both RAM and ROM using multiple RAM and ROM chips i n hardware. Finally, demonstrate the design of the magnetic disks <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/differenttypesofmemoryandhardwaredesignsoframandrom-210111172259-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Discussed the memory hierarchy, the characteristics of memory like location, unit of data transfer, access method, and performance. Then demonstrate the design of both RAM and ROM chip. Shows how to configure the memory unit composed of both RAM and ROM using multiple RAM and ROM chips i n hardware. Finally, demonstrate the design of the magnetic disks
Different types of memory and hardware designs of RAM and ROM from Prasenjit Dey
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Cache memory /slideshow/memory-organization-cache-memory/241198882 memoryorganizationcachememory-210111171412
Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.]]>

Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.]]>
Mon, 11 Jan 2021 17:14:12 GMT /slideshow/memory-organization-cache-memory/241198882 prasenjitdey15@slideshare.net(prasenjitdey15) Cache memory prasenjitdey15 Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/memoryorganizationcachememory-210111171412-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.
Cache memory from Prasenjit Dey
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Carry look ahead adder /slideshow/carry-look-ahead-adder-241198871/241198871 carrylookaheadadder-210111171224
Explain the drawbacks of Ripple carry adder, then derives the expression of Carry look ahead adder from Full Adder. After that, demonstrated the generalized expression of Carry look ahead adder. Finally, shows the hardware architecture of a Carry look ahead adder.]]>

Explain the drawbacks of Ripple carry adder, then derives the expression of Carry look ahead adder from Full Adder. After that, demonstrated the generalized expression of Carry look ahead adder. Finally, shows the hardware architecture of a Carry look ahead adder.]]>
Mon, 11 Jan 2021 17:12:24 GMT /slideshow/carry-look-ahead-adder-241198871/241198871 prasenjitdey15@slideshare.net(prasenjitdey15) Carry look ahead adder prasenjitdey15 Explain the drawbacks of Ripple carry adder, then derives the expression of Carry look ahead adder from Full Adder. After that, demonstrated the generalized expression of Carry look ahead adder. Finally, shows the hardware architecture of a Carry look ahead adder. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/carrylookaheadadder-210111171224-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Explain the drawbacks of Ripple carry adder, then derives the expression of Carry look ahead adder from Full Adder. After that, demonstrated the generalized expression of Carry look ahead adder. Finally, shows the hardware architecture of a Carry look ahead adder.
Carry look ahead adder from Prasenjit Dey
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Binary division restoration and non restoration algorithm /slideshow/binary-division-restoration-and-non-restoration-algorithm/241198836 binarydivisionrestorationandnon-restorationalgorithm-210111170816
Discussed basic approach of binary division, then restoring division and it's drawbacks and finally discussed non restoring division algorithm]]>

Discussed basic approach of binary division, then restoring division and it's drawbacks and finally discussed non restoring division algorithm]]>
Mon, 11 Jan 2021 17:08:16 GMT /slideshow/binary-division-restoration-and-non-restoration-algorithm/241198836 prasenjitdey15@slideshare.net(prasenjitdey15) Binary division restoration and non restoration algorithm prasenjitdey15 Discussed basic approach of binary division, then restoring division and it's drawbacks and finally discussed non restoring division algorithm <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/binarydivisionrestorationandnon-restorationalgorithm-210111170816-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Discussed basic approach of binary division, then restoring division and it&#39;s drawbacks and finally discussed non restoring division algorithm
Binary division restoration and non restoration algorithm from Prasenjit Dey
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Booth's algorithm /prasenjitdey15/booths-algorithm-241198779 boothsalgorithmwithoutaudio-210111170039
Different types of Binary Multiplication]]>

Different types of Binary Multiplication]]>
Mon, 11 Jan 2021 17:00:39 GMT /prasenjitdey15/booths-algorithm-241198779 prasenjitdey15@slideshare.net(prasenjitdey15) Booth's algorithm prasenjitdey15 Different types of Binary Multiplication <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/boothsalgorithmwithoutaudio-210111170039-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Different types of Binary Multiplication
Booth's algorithm from Prasenjit Dey
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