際際滷shows by User: redwanarnob / http://www.slideshare.net/images/logo.gif 際際滷shows by User: redwanarnob / Wed, 13 Jul 2016 05:52:33 GMT 際際滷Share feed for 際際滷shows by User: redwanarnob Final thesis presentation on bci /slideshow/final-thesis-presentation-on-bci-63974534/63974534 qmt5cozfqcqhaccghsww-signature-9e870f4384297638243a877fa3fd7a34e7c32d9e192b987c61bf72f72e945a84-poli-160713055233
My Thesis Topic was "Motor Imagery Signal Classification using EEG and ECoG signal for Brain Computer Interface." I have done my undergraduate thesis on the study, comparison and development of newer algorithms and feature sets related to two class classification problem in Motor Imagery Signal Classification using EEG and ECoG signal for Brain Computer Interface under the supervision of Dr. Mohammad Imamul Hassan Bhuiyan, Professor, Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology.]]>
My Thesis Topic was "Motor Imagery Signal Classification using EEG and ECoG signal for Brain Computer Interface." I have done my undergraduate thesis on the study, comparison and development of newer algorithms and feature sets related to two class classification problem in Motor Imagery Signal Classification using EEG and ECoG signal for Brain Computer Interface under the supervision of Dr. Mohammad Imamul Hassan Bhuiyan, Professor, Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology.]]> Wed, 13 Jul 2016 05:52:33 GMT /slideshow/final-thesis-presentation-on-bci-63974534/63974534 redwanarnob@slideshare.net(redwanarnob) Final thesis presentation on bci redwanarnob My Thesis Topic was "Motor Imagery Signal Classification using EEG and ECoG signal for Brain Computer Interface." I have done my undergraduate thesis on the study, comparison and development of newer algorithms and feature sets related to two class classification problem in Motor Imagery Signal Classification using EEG and ECoG signal for Brain Computer Interface under the supervision of Dr. Mohammad Imamul Hassan Bhuiyan, Professor, Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/qmt5cozfqcqhaccghsww-signature-9e870f4384297638243a877fa3fd7a34e7c32d9e192b987c61bf72f72e945a84-poli-160713055233-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> My Thesis Topic was &quot;Motor Imagery Signal Classification using EEG and ECoG signal for Brain Computer Interface.&quot; I have done my undergraduate thesis on the study, comparison and development of newer algorithms and feature sets related to two class classification problem in Motor Imagery Signal Classification using EEG and ECoG signal for Brain Computer Interface under the supervision of Dr. Mohammad Imamul Hassan Bhuiyan, Professor, Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology.
Final thesis presentation on bci from Redwan Islam
]]> 1678 3 https://cdn.slidesharecdn.com/ss_thumbnails/qmt5cozfqcqhaccghsww-signature-9e870f4384297638243a877fa3fd7a34e7c32d9e192b987c61bf72f72e945a84-poli-160713055233-thumbnail.jpg?width=120&height=120&fit=bounds presentation 000000 http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Designing a uniform filter bank using multirate concept /slideshow/designing-a-uniform-filter-bank-using-multirate-concept/63974390 dsp2completepresentation-160713054630
This presentation was created as a part of our Digital SIgnal Processing II course. The presentation is about designing a uniform filter bank using multirate concept. The presentation contains the main algorithm and subsequent MATLAB plots for for creating a uniform filter bank from a single filter prototype using multirate signal processing technique ]]>
This presentation was created as a part of our Digital SIgnal Processing II course. The presentation is about designing a uniform filter bank using multirate concept. The presentation contains the main algorithm and subsequent MATLAB plots for for creating a uniform filter bank from a single filter prototype using multirate signal processing technique ]]> Wed, 13 Jul 2016 05:46:30 GMT /slideshow/designing-a-uniform-filter-bank-using-multirate-concept/63974390 redwanarnob@slideshare.net(redwanarnob) Designing a uniform filter bank using multirate concept redwanarnob This presentation was created as a part of our Digital SIgnal Processing II course. The presentation is about designing a uniform filter bank using multirate concept. The presentation contains the main algorithm and subsequent MATLAB plots for for creating a uniform filter bank from a single filter prototype using multirate signal processing technique <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/dsp2completepresentation-160713054630-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> This presentation was created as a part of our Digital SIgnal Processing II course. The presentation is about designing a uniform filter bank using multirate concept. The presentation contains the main algorithm and subsequent MATLAB plots for for creating a uniform filter bank from a single filter prototype using multirate signal processing technique
Designing a uniform filter bank using multirate concept from Redwan Islam
]]> 621 1 https://cdn.slidesharecdn.com/ss_thumbnails/dsp2completepresentation-160713054630-thumbnail.jpg?width=120&height=120&fit=bounds presentation 000000 http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Vlsi ii project presentation /slideshow/vlsi-ii-project-presentation/63974116 jnfzjmswsuelwjbq1rsw-signature-98e46c330c5560a9270b3c81d7b0631e4a8de6520efe70702d9e731b785f8b3c-poli-160713053329
We completed the Top down and Bottom Up design and layout of an n-bit general purpose shift register using Cadence Encounter RTL & Cadence Virtuoso Design Environment respectively in our VLSI II Laboratory. For the purpose of demonstration, we chose n=4. The Top down approach was completed upto generating synthesized Verilog code since the technology files required to do the layout was not available in our laboratory. However, we completed the Bottom up approach completely with an additional ESD protection circuit in order to ensure a better protection to the inner core of the chip. ]]>
We completed the Top down and Bottom Up design and layout of an n-bit general purpose shift register using Cadence Encounter RTL & Cadence Virtuoso Design Environment respectively in our VLSI II Laboratory. For the purpose of demonstration, we chose n=4. The Top down approach was completed upto generating synthesized Verilog code since the technology files required to do the layout was not available in our laboratory. However, we completed the Bottom up approach completely with an additional ESD protection circuit in order to ensure a better protection to the inner core of the chip. ]]> Wed, 13 Jul 2016 05:33:29 GMT /slideshow/vlsi-ii-project-presentation/63974116 redwanarnob@slideshare.net(redwanarnob) Vlsi ii project presentation redwanarnob We completed the Top down and Bottom Up design and layout of an n-bit general purpose shift register using Cadence Encounter RTL & Cadence Virtuoso Design Environment respectively in our VLSI II Laboratory. For the purpose of demonstration, we chose n=4. The Top down approach was completed upto generating synthesized Verilog code since the technology files required to do the layout was not available in our laboratory. However, we completed the Bottom up approach completely with an additional ESD protection circuit in order to ensure a better protection to the inner core of the chip. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/jnfzjmswsuelwjbq1rsw-signature-98e46c330c5560a9270b3c81d7b0631e4a8de6520efe70702d9e731b785f8b3c-poli-160713053329-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> We completed the Top down and Bottom Up design and layout of an n-bit general purpose shift register using Cadence Encounter RTL &amp; Cadence Virtuoso Design Environment respectively in our VLSI II Laboratory. For the purpose of demonstration, we chose n=4. The Top down approach was completed upto generating synthesized Verilog code since the technology files required to do the layout was not available in our laboratory. However, we completed the Bottom up approach completely with an additional ESD protection circuit in order to ensure a better protection to the inner core of the chip.
Vlsi ii project presentation from Redwan Islam
]]> 546 4 https://cdn.slidesharecdn.com/ss_thumbnails/jnfzjmswsuelwjbq1rsw-signature-98e46c330c5560a9270b3c81d7b0631e4a8de6520efe70702d9e731b785f8b3c-poli-160713053329-thumbnail.jpg?width=120&height=120&fit=bounds presentation 000000 http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Biomedical Instrumentation Presentation on Infrared Emitter-Detector and Arduino based low cost Heart Rate Monitor /slideshow/biomedical-instrumentation-presentation-on-infrared-emitterdetector-and-arduino-based-low-cost-heart-rate-monitor/59999817 8ft7dws8sdmpappufati-signature-fb8036ceb24fb52e728590870939c441c474abf952dc476ba0e2cc61e630df5d-poli-160324175554
In this project, we measured human heart rate using IR emitter and detector, Arduino board and some other low cost component. We observed heart rate of some individuals with IR emitter and detector, Arduino Board and Processing 2.0 software, and attached the result in the report. We compared the cost of heart rate monitor that uses IR emitter and detector, and the one that uses pulse sensor. ]]>
In this project, we measured human heart rate using IR emitter and detector, Arduino board and some other low cost component. We observed heart rate of some individuals with IR emitter and detector, Arduino Board and Processing 2.0 software, and attached the result in the report. We compared the cost of heart rate monitor that uses IR emitter and detector, and the one that uses pulse sensor. ]]> Thu, 24 Mar 2016 17:55:54 GMT /slideshow/biomedical-instrumentation-presentation-on-infrared-emitterdetector-and-arduino-based-low-cost-heart-rate-monitor/59999817 redwanarnob@slideshare.net(redwanarnob) Biomedical Instrumentation Presentation on Infrared Emitter-Detector and Arduino based low cost Heart Rate Monitor redwanarnob In this project, we measured human heart rate using IR emitter and detector, Arduino board and some other low cost component. We observed heart rate of some individuals with IR emitter and detector, Arduino Board and Processing 2.0 software, and attached the result in the report. We compared the cost of heart rate monitor that uses IR emitter and detector, and the one that uses pulse sensor. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/8ft7dws8sdmpappufati-signature-fb8036ceb24fb52e728590870939c441c474abf952dc476ba0e2cc61e630df5d-poli-160324175554-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> In this project, we measured human heart rate using IR emitter and detector, Arduino board and some other low cost component. We observed heart rate of some individuals with IR emitter and detector, Arduino Board and Processing 2.0 software, and attached the result in the report. We compared the cost of heart rate monitor that uses IR emitter and detector, and the one that uses pulse sensor.
Biomedical Instrumentation Presentation on Infrared Emitter-Detector and Arduino based low cost Heart Rate Monitor from Redwan Islam
]]> 1303 5 https://cdn.slidesharecdn.com/ss_thumbnails/8ft7dws8sdmpappufati-signature-fb8036ceb24fb52e728590870939c441c474abf952dc476ba0e2cc61e630df5d-poli-160324175554-thumbnail.jpg?width=120&height=120&fit=bounds presentation 000000 http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 https://cdn.slidesharecdn.com/profile-photo-redwanarnob-48x48.jpg?cb=1617595452 I am Md. Redwan Islam and I'm a B.Sc. in EEE from BUET. I live in Mirpur with my parents and a younger brother. I would like to develop my career as in Electrical, Electronic, Communication Engineering along with R&D and data processing & software engineering using my B.Sc. Engineering knowledge on EEE from BUET in VLSI, mobile cellular and telecommunication engineering, optical fiber communication, Digital, Random and bio signals processing, Biomedical instrumentation, solid state devices & power system and electrical energy conversion. https://cdn.slidesharecdn.com/ss_thumbnails/qmt5cozfqcqhaccghsww-signature-9e870f4384297638243a877fa3fd7a34e7c32d9e192b987c61bf72f72e945a84-poli-160713055233-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/final-thesis-presentation-on-bci-63974534/63974534 Final thesis presentat... https://cdn.slidesharecdn.com/ss_thumbnails/dsp2completepresentation-160713054630-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/designing-a-uniform-filter-bank-using-multirate-concept/63974390 Designing a uniform fi... https://cdn.slidesharecdn.com/ss_thumbnails/jnfzjmswsuelwjbq1rsw-signature-98e46c330c5560a9270b3c81d7b0631e4a8de6520efe70702d9e731b785f8b3c-poli-160713053329-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/vlsi-ii-project-presentation/63974116 Vlsi ii project presen...