際際滷shows by User: vitaliykulanov / http://www.slideshare.net/images/logo.gif 際際滷shows by User: vitaliykulanov / Sun, 14 May 2017 20:16:32 GMT 際際滷Share feed for 際際滷shows by User: vitaliykulanov File input/output in VHDL /slideshow/file-inputoutput-in-vhdl/75966713 lecturevhdlfileio-170514201632
The lecture is about file I/O in VHDL: basic steps, syntax, declaration, TEXTIO package, file handler, file descriptor, file type]]>
The lecture is about file I/O in VHDL: basic steps, syntax, declaration, TEXTIO package, file handler, file descriptor, file type]]> Sun, 14 May 2017 20:16:32 GMT /slideshow/file-inputoutput-in-vhdl/75966713 vitaliykulanov@slideshare.net(vitaliykulanov) File input/output in VHDL vitaliykulanov The lecture is about file I/O in VHDL: basic steps, syntax, declaration, TEXTIO package, file handler, file descriptor, file type <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlfileio-170514201632-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about file I/O in VHDL: basic steps, syntax, declaration, TEXTIO package, file handler, file descriptor, file type
File input/output in VHDL from vitaliykulanov
]]> 2376 2 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlfileio-170514201632-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Subprograms in VHDL, Functions in VHDL /slideshow/subprograms-in-vhdl-functions-in-vhdl/75966624 lecturevhdlfunctions-170514201021
The lecture is about functions in VHDL: syntax, declaration, area of application, function overloading , overloading of operator symbols.]]>
The lecture is about functions in VHDL: syntax, declaration, area of application, function overloading , overloading of operator symbols.]]> Sun, 14 May 2017 20:10:21 GMT /slideshow/subprograms-in-vhdl-functions-in-vhdl/75966624 vitaliykulanov@slideshare.net(vitaliykulanov) Subprograms in VHDL, Functions in VHDL vitaliykulanov The lecture is about functions in VHDL: syntax, declaration, area of application, function overloading , overloading of operator symbols. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlfunctions-170514201021-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about functions in VHDL: syntax, declaration, area of application, function overloading , overloading of operator symbols.
Subprograms in VHDL, Functions in VHDL from vitaliykulanov
]]> 1211 2 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlfunctions-170514201021-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Subprograms in VHDL, Procedures in VHDL /slideshow/subprograms-in-vhdl-procedures-in-vhdl/75966492 lecturevhdlprocedures-170514200111
The lecture is about procedures in VHDL: syntax, declaration, actual parameters, formal parameters, procedure overloading]]>
The lecture is about procedures in VHDL: syntax, declaration, actual parameters, formal parameters, procedure overloading]]> Sun, 14 May 2017 20:01:10 GMT /slideshow/subprograms-in-vhdl-procedures-in-vhdl/75966492 vitaliykulanov@slideshare.net(vitaliykulanov) Subprograms in VHDL, Procedures in VHDL vitaliykulanov The lecture is about procedures in VHDL: syntax, declaration, actual parameters, formal parameters, procedure overloading <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlprocedures-170514200111-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about procedures in VHDL: syntax, declaration, actual parameters, formal parameters, procedure overloading
Subprograms in VHDL, Procedures in VHDL from vitaliykulanov
]]> 1083 2 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlprocedures-170514200111-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Structural project description in VHDL /slideshow/structural-project-description-in-vhdl/75966212 lecturevhdlstructuralapproach-170514194022
The lecture is about structural description of projects in VHDL: component declaration, component instantiation, for...generate, if...generate statements]]>
The lecture is about structural description of projects in VHDL: component declaration, component instantiation, for...generate, if...generate statements]]> Sun, 14 May 2017 19:40:22 GMT /slideshow/structural-project-description-in-vhdl/75966212 vitaliykulanov@slideshare.net(vitaliykulanov) Structural project description in VHDL vitaliykulanov The lecture is about structural description of projects in VHDL: component declaration, component instantiation, for...generate, if...generate statements <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlstructuralapproach-170514194022-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about structural description of projects in VHDL: component declaration, component instantiation, for...generate, if...generate statements
Structural project description in VHDL from vitaliykulanov
]]> 1170 3 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlstructuralapproach-170514194022-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Statements in VHDL - Concurrent Statements /slideshow/statements-in-vhdl-concurrent-statements/75966094 lecturevhdlconcurrentoperators-170514193213
The lecture is about Concurrent Statements in VHDL: operators, principles of work, examples.]]>
The lecture is about Concurrent Statements in VHDL: operators, principles of work, examples.]]> Sun, 14 May 2017 19:32:12 GMT /slideshow/statements-in-vhdl-concurrent-statements/75966094 vitaliykulanov@slideshare.net(vitaliykulanov) Statements in VHDL - Concurrent Statements vitaliykulanov The lecture is about Concurrent Statements in VHDL: operators, principles of work, examples. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlconcurrentoperators-170514193213-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about Concurrent Statements in VHDL: operators, principles of work, examples.
Statements in VHDL - Concurrent Statements from vitaliykulanov
]]> 819 2 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlconcurrentoperators-170514193213-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Statements in VHDL - Sequential Statements /slideshow/statements-in-vhdl-sequential-statements/75965954 lecturevhdloperatorssequentialoperators-170514192142
The lecture is about statements in VHDL - classification and principles of work. Sequential statements (operators) in VHDL: principles, operators, examples]]>
The lecture is about statements in VHDL - classification and principles of work. Sequential statements (operators) in VHDL: principles, operators, examples]]> Sun, 14 May 2017 19:21:42 GMT /slideshow/statements-in-vhdl-sequential-statements/75965954 vitaliykulanov@slideshare.net(vitaliykulanov) Statements in VHDL - Sequential Statements vitaliykulanov The lecture is about statements in VHDL - classification and principles of work. Sequential statements (operators) in VHDL: principles, operators, examples <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdloperatorssequentialoperators-170514192142-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about statements in VHDL - classification and principles of work. Sequential statements (operators) in VHDL: principles, operators, examples
Statements in VHDL - Sequential Statements from vitaliykulanov
]]> 1046 2 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdloperatorssequentialoperators-170514192142-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Basic principles of projects description in VHDL - ENTITY, ARCHITECTURE, LIBRARY, PACKAGE /slideshow/basic-principles-of-projects-description-in-vhdl-entity-architecture-library-package/75965845 lecturevhdlentityarchitecturegenericpackages-170514191450
The lecture is about main principles of projects description in VHDL. Elements of project design unit: ENTITY, ARCHITECTURE, PACKAGE, LIBRARY]]>
The lecture is about main principles of projects description in VHDL. Elements of project design unit: ENTITY, ARCHITECTURE, PACKAGE, LIBRARY]]> Sun, 14 May 2017 19:14:50 GMT /slideshow/basic-principles-of-projects-description-in-vhdl-entity-architecture-library-package/75965845 vitaliykulanov@slideshare.net(vitaliykulanov) Basic principles of projects description in VHDL - ENTITY, ARCHITECTURE, LIBRARY, PACKAGE vitaliykulanov The lecture is about main principles of projects description in VHDL. Elements of project design unit: ENTITY, ARCHITECTURE, PACKAGE, LIBRARY <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlentityarchitecturegenericpackages-170514191450-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about main principles of projects description in VHDL. Elements of project design unit: ENTITY, ARCHITECTURE, PACKAGE, LIBRARY
Basic principles of projects description in VHDL - ENTITY, ARCHITECTURE, LIBRARY, PACKAGE from vitaliykulanov
]]> 1129 2 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlentityarchitecturegenericpackages-170514191450-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Attributes in VHDL /vitaliykulanov/attributes-in-vhdl-75965729 lecturevhdlattributes-170514190653
The lecture is about attributes in VHDL, attributes of signals, variables and arrays, user-defined attributes]]>
The lecture is about attributes in VHDL, attributes of signals, variables and arrays, user-defined attributes]]> Sun, 14 May 2017 19:06:53 GMT /vitaliykulanov/attributes-in-vhdl-75965729 vitaliykulanov@slideshare.net(vitaliykulanov) Attributes in VHDL vitaliykulanov The lecture is about attributes in VHDL, attributes of signals, variables and arrays, user-defined attributes <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlattributes-170514190653-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about attributes in VHDL, attributes of signals, variables and arrays, user-defined attributes
Attributes in VHDL from vitaliykulanov
]]> 1037 0 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlattributes-170514190653-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 VHDL composite data types, arrays, records /slideshow/vhdl-composite-data-types-arrays-records/75965582 lecturevhdlarraysrecords-170514185649
The lecture is about composite data types in VHDL: arrays and records.]]>
The lecture is about composite data types in VHDL: arrays and records.]]> Sun, 14 May 2017 18:56:49 GMT /slideshow/vhdl-composite-data-types-arrays-records/75965582 vitaliykulanov@slideshare.net(vitaliykulanov) VHDL composite data types, arrays, records vitaliykulanov The lecture is about composite data types in VHDL: arrays and records. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlarraysrecords-170514185649-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about composite data types in VHDL: arrays and records.
VHDL composite data types, arrays, records from vitaliykulanov
]]> 1341 2 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlarraysrecords-170514185649-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 VHDL data types, user-defined types, subtypes /slideshow/vhdl-data-types-userdefined-types-subtypes/75963180 lecturevhdldatatypes-170514161917
The lecture is about data types in VHDL, how to create user defined types and subtypes in VHDL]]>
The lecture is about data types in VHDL, how to create user defined types and subtypes in VHDL]]> Sun, 14 May 2017 16:19:17 GMT /slideshow/vhdl-data-types-userdefined-types-subtypes/75963180 vitaliykulanov@slideshare.net(vitaliykulanov) VHDL data types, user-defined types, subtypes vitaliykulanov The lecture is about data types in VHDL, how to create user defined types and subtypes in VHDL <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdldatatypes-170514161917-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> The lecture is about data types in VHDL, how to create user defined types and subtypes in VHDL
VHDL data types, user-defined types, subtypes from vitaliykulanov
]]> 1061 2 https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdldatatypes-170514161917-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 https://cdn.slidesharecdn.com/profile-photo-vitaliykulanov-48x48.jpg?cb=1616530611 ci.csn.khai.edu https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlfileio-170514201632-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/file-inputoutput-in-vhdl/75966713 File input/output in VHDL https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlfunctions-170514201021-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/subprograms-in-vhdl-functions-in-vhdl/75966624 Subprograms in VHDL, F... https://cdn.slidesharecdn.com/ss_thumbnails/lecturevhdlprocedures-170514200111-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/subprograms-in-vhdl-procedures-in-vhdl/75966492 Subprograms in VHDL, P...