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Subprograms in VHDL, Procedures in VHDL

vitaliykulanov
vitaliykulanov

The lecture is about procedures in VHDL: syntax, declaration, actual parameters, formal parameters, procedure overloading

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仍舒仆仂于 .. [v.kulanov@csn.khai.edu] 仂亟仗仂亞舒仄仄. 仂亠亟 于 磶从亠 VHDL 束丐亠仆仂仍仂亞亳亳 仗仂亠从亳仂于舒仆亳 从仂仄仗ﾑ亠仆 亳亠仄損
仂亟仗仂亞舒仄仄丿仂, 仂仗 仗仂亟仗仂亞舒仄仄? 弍亠仗亠亳于舒ﾑ 从亳亰舒亳 仂仗亳舒仆亳 仗仂亠从舒 仗亠仄 舒亰亟亠仍亠仆亳 亠亞仂 仆舒 舒仄仂仂亠仍仆亠 弍仍仂从亳 亰舒亟舒仆仆仂亶 仆从亳仂仆舒仍仆仂 仂亰于仂仍ﾑ 亰舒仄亠仆亳 仆亠从仂仍从仂 仂仗亳舒仆亳亶 仂亟仆 舒亞仄亠仆仂于 舒仍亞仂亳仄舒 仂亟仆亳仄 仂弍磦仍亠仆亳亠仄 仗仂亟仗仂亞舒仄仄 亳 仆亠仂弍仂亟亳仄仄 从仂仍亳亠于仂仄 亠 于亰仂于仂于 于 仂仆仂于仆仂仄 亠从亠 仗仂亠从舒 舒亰仍亳舒ﾑ 亟于舒 于亳亟舒 仗仂亟仗仂亞舒仄仄 仗仂亠亟 (PROCEDURE) 仆从亳亳 (FUNCTION)
仂亠亟 于 VHDL PROCEDURE name[(parameter_interface_list)] IS {subprogram_declarative_item} BEGIN {sequential_statement} END [PROCEDURE] [name]; SIGNAL, TYPE, FILE, SUBTYPE, PROCEDURE, FUNCTION, VARIABLE, COMPONENT, CONSTANT ...-- 仗仂仍亠亟仂于舒亠仍仆亠 仂仗亠舒仂 a := 5 FOR LOOP END LOOP; ... IF THEN ELSE END IF; 仄 仗仂亠亟 弌仗亳仂从 仂仄舒仍仆 仗舒舒仄亠仂于 (仄仂亢亠 仂于仂于舒)
project_pkg.vhd n_reg.vhd 弍磦仍亠仆亳亠 仗仂亠亟 -- USE work.project_pkg; ENTITY reg_file IS GENERIC (...); PORT (...); END ENTITY n_reg; ARCHITECTURE rtl OF reg_file IS BEGIN PROCESS(...) BEGIN ... END PROCESS; ... END; PROCEDURE inc(a: INOUT INTEGER; step: INTEGER := 1) IS BEGIN a := a + step; END PROCEDURE inc; ... PACKAGE project_pkg IS ... PROCEDURE inc(a: INOUT INTEGER; step: INTEGER := 1); ... END PACKAGE project_pkg; PACKAGE BODY project_pkg IS END PACKAGE BODY project_pkg; ... ... 舒仍亳亳亠 仗仂仂亳仗舒 仗仂亟仗仂亞舒仄仄 仆亠仂弍磶舒亠仍仆仂, 仆仂 亠从仂仄亠仆亟亠
弌仗亳仂从 仗舒舒仄亠仂于 仗仂亠亟 PROCEDURE name[(parameter_interface_list)] IS ... ([CONSTANT|VARIABLE|SIGNAL] identifier {,}: [IN|OUT|INOUT] type_indication [:= expression] {;}) 仄/亟亠仆亳亳从舒仂 仗舒舒仄亠舒 仍舒 仗舒舒仄亠舒 (仄仂亢亠 弍 亠亠 FILE) 亳亟 仗舒舒仄亠舒 丐亳仗 仗舒舒仄亠舒 仆舒亠仆亳亠 仗仂 仄仂仍舒仆亳. 仂亢亠 弍 亰舒亟舒仆仂 仂仍从仂 亟仍 仗舒舒仄亠仂于 从仍舒舒 CONSTANT 亳 VARIABLE PROCEDURE foo(val: INTEGER) -- val - CONSTANT PROCEDURE foo(val: IN INTEGER) -- val - CONSTANT PROCEDURE foo(val, bar: OUT INTEGER) -- val, bar - VARIABLE PROCEDURE foo(val: INOUT INTEGER) -- val VARIABLE
亰仂于 仗仂亠亟 于 VHDL 亰仂于 仗仂亠亟 亰舒仗亳于舒亠 于 亳仂亟仆仂仄 从仂亟亠 从舒从 仂亟亠仍仆亶 仂仗亠舒仂, 从仂仂亶 亳仄亠亠 仍亠亟ﾑ亳亶 亳仆舒从亳: [label:] name [(parameter_list)]; 亠从舒 弌仗亳仂从 舒从亳亠从亳 仗舒舒仄亠仂于 ([parameter_name =>] expression|signal_name|variable_name|OPEN, {}) 个仂仄舒仍仆亶 仗舒舒仄亠 于舒 亳仗舒 仂仗仂舒于仍亠仆亳: 仄亠仆仂于舒仆仆仂亠 (=>) 仂亰亳亳仂仆仆仂亠 个舒从亳亠从亳亶 仗舒舒仄亠 舒亢亠仆亳亠/仂仆舒仆仆仂亠 亰仆舒亠仆亳亠 弌亳亞仆舒仍 亠亠仄亠仆仆舒 仍ﾑ亠于仂亠 仍仂于仂 OPEN - 仆亠 亳仗仂仍亰亠 亳仍亳 亰仆舒亠仆亳亠 仗仂 仄仂仍舒仆亳
仂亠亟 于 VHDL 仍亳 亳仗仂仍亰亠 仄亠舒仆仆亶 亳仗 仂仗仂舒于仍亠仆亳 仗舒舒仄亠仂于 仂亞亟舒, 亳仄亠仆仂于舒仆仆仂亠 仂仗仂舒于仍亠仆亳亠 于 仗亳从亠 仗舒舒仄亠仂于 亟仂仍亢仆仂 于亠亞亟舒 弍 仗仂仍亠亟仆亳仄: do_smth(good, more => 1, even_more => 2); do_smth(bad, more => 1, 2); -- 仆舒亠仆 仗仂磲仂从 舒舒仄亠-从仂仆舒仆 亳 仗舒舒仄亠-仗亠亠仄亠仆仆亠 仗亠亠亟舒ﾑ 于/亳亰 仗仂亠亟 仗仂 亰仆舒亠仆亳 亳 于亰仂于亠 仗仂亠亟 仗舒舒仄亠仂仄 亳亞仆舒仍仂仄 仗仂亳仂亟亳 仗亠亠亟舒舒 仗舒舒仄亠舒 仆亠 仗仂 亰仆舒亠仆亳, 舒 仗仂 仍从亠: 亰仆舒亠仆亳亠 亳亞仆舒仍舒 仄仂亢亠 仄亠仆 仆亠 仂仍从仂 于 亠亰仍舒亠 于仗仂仍仆磳仄 于 仗仂亠亟亠 亟亠亶于亳亶, 仆仂 亳 于 亠亰仍舒亠 亟亠亶于亳亶, 于仗仂仍仆磳仄 仗舒舒仍仍亠仍仆仂 仆亠亶 (亟亞亳仄亳 仗仂亠舒仄亳, 仗舒舒仍仍亠仍仆仄亳 仂仗亠舒仂舒仄亳)
仂亠亟 于 VHDL 仍亳 亳仗仂仍亰亠 仂仄舒仍仆亶 仗舒舒仄亠-亳亞仆舒仍 于亳亟舒 OUT, 仂 亳亰仄亠仆亠仆亳亠 亰仆舒亠仆亳 仂亞仂 仗舒舒仄亠舒 于 仗仂亠亟亠 于仍亠亠 亰舒 仂弍仂亶 亳亰仄亠仆亠仆亳亠 亰仆舒亠仆亳 仂仂于亠于ﾑ亠亞仂 亠仄 舒从亳亠从仂亞仂 仗舒舒仄亠舒 亳亞仆舒仍舒 于 于亰于舒于亠仄 仗仂亠亟 仗仂亠亠 个仂仄舒仍仆亠 仗舒舒仄亠-亳亞仆舒仍 舒从亢亠 仄仂亞 亳仄亠 于亳亟 INOUT. 仂仄 仍舒亠 于 从舒亠于亠 舒从亳亠从仂亞仂 仗舒舒仄亠舒 亟仂仍亢亠仆 于仗舒 亳亞仆舒仍, 于仆亠仆亳亶 从 仂弍亠从 仄仂亟亠仍亳仂于舒仆亳, 舒 仆亠 仂仗亳舒仆仆亶 于仆亳 仆亠亞仂 从舒亠于亠 从仍舒舒 (仂弍亠从舒) 仗舒舒仄亠舒 仄仂亞 于仗舒 FILE, 于 舒从仂仄 仍舒亠 于亳亟 仗舒舒仄亠舒 (IN, OUT, INOUT) 仆亠 从舒亰于舒亠: PROCEDURE writeline(FILE f: text; l: INOUT line);
仂亠亟 于 VHDL 仂弍亠仄 于亳亟亠 仗仂亠亟 磦仍ﾑ 束亳仆亠亰亳亠仄仄亳損, 亠仍亳 仂仆亳 仆亠 仂亟亠亢舒 于 于仂亠仄 亠仍亠 仂仗亠舒仂 WAIT: 亠仍亳 于 亠仍亠 仗仂亠亟 亳仗仂仍亰亠 仂仗亠舒仂 WAIT, 仂 于亰仂于 仗仂亠亟 亳亰 仆从亳亳 仆亠亟仂仗亳仄, 舒 于亰仂于 亳亰 亠仍舒 仂仗亠舒仂舒 PROCESS 于仂亰仄仂亢亠仆 于 仍舒亠, 亠仍亳 仂仗亠舒仂 PROCESS 仆亠 仂亟亠亢亳 仗亳从舒 于于亳亠仍仆仂亳 亠亠仄亠仆仆亠, 仂弍磦仍亠仆仆亠 于 仗仂亟仗仂亞舒仄仄亠 亳仆亳亳舒仍亳亰亳ﾑ 亰舒仆仂于仂 仗亳 从舒亢亟仂仄 于亰仂于亠 仗仂亠亟 仂亰仄仂亢亠仆 亠从亳于仆亶 于亰仂于 仗仂亠亟 仆亠 于亠亞亟舒 束亳仆亠亰亳亠晛 仂亰仄仂亢仆仂 亳仗仂仍亰仂于舒仆亳亠 仄亠舒仆亳亰仄舒 束仗亠亠亞亰从亳損 仗仂亠亟 于亰仂于 仂仂于亠于ﾑ亠亶 仂仗亠亟亠仍磳 亳仂亟 亳亰 仆舒弍仂舒 (从仂仍亳亠于舒) 亳 亳仗舒 舒从亳亠从亳 仗舒舒仄亠仂于
仂亠亟 于 VHDL CONSTANT VARIABLE ARCHITECTURE rtl OF example IS PROCEDURE inc(a: INOUT INTEGER; step: INTEGER := 1) IS BEGIN a := a + step; END PROCEDURE inc; BEGIN name : PROCESS IS VARIABLE v: INTEGER := 0; BEGIN REPORT "v = " & INTEGER'IMAGE(v) SEVERITY NOTE; inc(v); -- a := a + 1 v = 1 WAIT FOR 10 ns; inc(a => v, step => 2); -- a := a + 2 v = 3 WAIT FOR 10 ns; inc(v, step => 2 + 3); -- a := a + 2 + 3 v = 8 END PROCESS name; END ARCHITECTURE rtl;
仂亠亟 于 VHDL PROCEDURE convert(SIGNAL sel: IN BIT_VECTOR (0 TO 1); SIGNAL val : OUT BIT) IS BEGIN CASE sel IS WHEN "00" | "11" => val <= '1'; WHEN OTHERS => val <= '0'; END CASE; END PROCEDURE convert; ... convert(sel => addr, val => data); -- convert(addr, data); ... -- 亠舒仍亳亰舒亳 XNOR
仂亠亟 于 VHDL ARCHITECTURE rtl OF adder IS PROCEDURE addu(a, b: IN STD_LOGIC_VECTOR(N - 1 DOWNTO 0); signal res: OUT STD_LOGIC_VECTOR(N - 1 DOWNTO 0)) IS VARIABLE sum: STD_LOGIC_VECTOR(N - 1 DOWNTO 0); VARIABLE carry: STD_LOGIC := '0'; BEGIN FOR index IN sum'reverse_range LOOP sum(index) := a(index) XOR b(index) XOR carry; carry := (a(index) AND b(index)) OR (carry AND (a(index) XOR b(index))); END LOOP; result <= sum; END PROCEDURE addu; BEGIN addu(a => data_a, b => data_b, res => res); END ARCHITECTURE rtl; N = 1 N = 2
仂亠亟 于 VHDL ARCHITECTURE rtl OF adder IS PROCEDURE addu(a, b: IN STD_LOGIC_VECTOR(N - 1 DOWNTO 0); signal res: OUT STD_LOGIC_VECTOR(N - 1 DOWNTO 0)) IS ... -- 仄仂亳 仗亠亟亟亳亶 仍舒亶亟 BEGIN ... -- 仄仂亳 仗亠亟亟亳亶 仍舒亶亟 END PROCEDURE addu; BEGIN reg : PROCESS (clk) IS BEGIN IF rising_edge(clk) THEN addu(data_a, data_b, res); END IF; END PROCESS reg; END ARCHITECTURE rtl; N = 1 N = 2
仂亠亟 于 VHDL SIGNAL en: STD_LOGIC; ... convert(sel => addr, val => en); reg : PROCESS (clk, en) IS begin IF rising_edge(clk) THEN if en = '1' THEN addu(a => data_a, b => data_b, res => res); END IF; END IF; END PROCESS reg;
仂亠亟 于 VHDL 亠仍亠 仗仂亠亟 仄仂亢亠 亳仗仂仍亰仂于舒 仂仗亠舒仂 RETURN, 仆舒亰仆舒亠仆亳亠 从仂仂仂亞仂 亰舒于亠亠仆亳亠 于仗仂仍仆亠仆亳 仗仂亠亟: [label:] RETURN; PROCEDURE sort2(VARIABLE x1,x2: INOUT INTEGER) IS VARIABLE t: INTEGER; BEGIN IF x1 > x2 THEN RETURN; ELSE t := x1; x1 := x2; x2 := t; END IF; END PROCEDURE; 舒从 仂 亟亠仍舒 弍亠亰 亟仂仗仂仍仆亳亠仍仆仂亶 仗亠亠仄亠仆仆仂亶 "t"?
亠亠亞亰从舒 仗仂亠亟 -- 仗仂仂亳仗 仗仂亠亟 inc PROCEDURE inc (a: INOUT word32; by: IN word32 := X"000_0001"); PROCEDURE inc (a: INOUT STD_LOGIC_VECTOR; by: IN STD_LOGIC_VECTOR := X"000_0001"); -- 仂仄舒仍仆仄亳 仗舒舒仄亠舒仄亳 仄仂亞 于仗舒 仄舒亳于 -- 仆亠仂亞舒仆亳亠仆仆仂亶 亟仍亳仆, 仆仂 仗亳 于亰仂于亠 仗仂亠亟 亟仍 仆亳 -- 亟仂仍亢仆 弍 仂仗亠亟亠仍亠仆 舒从亳亠从亳亠 亰仆舒亠仆亳亠 于 仂亞仂 -- 仂亞舒仆亳亠仆仆仂仄 亟亳舒仗舒亰仂仆亠 PROCEDURE inc (a, b: IN STD_LOGIC_VECTOR; by: IN STD_LOGIC_VECTOR := X"000_0001"); PROCEDURE inc (a: INOUT INTEGER; by: IN INTEGER := 1); -- 仗仂亰亳亳仂仆仆仂亠 仂仗仂舒于仍亠仆亳亠, 于 亰舒于亳亳仄仂亳 仂 亳仗舒 -- 亟舒仆仆 count 弍亟亠 于亰于舒仆舒 仂仂于亠于ﾑ舒 仗仂亠亟舒 inc(count); -- 亳仄亠仆仂于舒仆仆仂亠 仂仗仂舒于仍亠仆亳亠 inc(a => count, by => open) inc(a => count)
Subprograms in VHDL, Procedures in VHDL

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Subprograms in VHDL, Procedures in VHDL

  • 1. 仍舒仆仂于 .. [v.kulanov@csn.khai.edu] 仂亟仗仂亞舒仄仄. 仂亠亟 于 磶从亠 VHDL 束丐亠仆仂仍仂亞亳亳 仗仂亠从亳仂于舒仆亳 从仂仄仗ﾑ亠仆 亳亠仄損
  • 2. 仂亟仗仂亞舒仄仄丿仂, 仂仗 仗仂亟仗仂亞舒仄仄? 弍亠仗亠亳于舒ﾑ 从亳亰舒亳 仂仗亳舒仆亳 仗仂亠从舒 仗亠仄 舒亰亟亠仍亠仆亳 亠亞仂 仆舒 舒仄仂仂亠仍仆亠 弍仍仂从亳 亰舒亟舒仆仆仂亶 仆从亳仂仆舒仍仆仂 仂亰于仂仍ﾑ 亰舒仄亠仆亳 仆亠从仂仍从仂 仂仗亳舒仆亳亶 仂亟仆 舒亞仄亠仆仂于 舒仍亞仂亳仄舒 仂亟仆亳仄 仂弍磦仍亠仆亳亠仄 仗仂亟仗仂亞舒仄仄 亳 仆亠仂弍仂亟亳仄仄 从仂仍亳亠于仂仄 亠 于亰仂于仂于 于 仂仆仂于仆仂仄 亠从亠 仗仂亠从舒 舒亰仍亳舒ﾑ 亟于舒 于亳亟舒 仗仂亟仗仂亞舒仄仄 仗仂亠亟 (PROCEDURE) 仆从亳亳 (FUNCTION)
  • 3. 仂亠亟 于 VHDL PROCEDURE name[(parameter_interface_list)] IS {subprogram_declarative_item} BEGIN {sequential_statement} END [PROCEDURE] [name]; SIGNAL, TYPE, FILE, SUBTYPE, PROCEDURE, FUNCTION, VARIABLE, COMPONENT, CONSTANT ...-- 仗仂仍亠亟仂于舒亠仍仆亠 仂仗亠舒仂 a := 5 FOR LOOP END LOOP; ... IF THEN ELSE END IF; 仄 仗仂亠亟 弌仗亳仂从 仂仄舒仍仆 仗舒舒仄亠仂于 (仄仂亢亠 仂于仂于舒)
  • 4. project_pkg.vhd n_reg.vhd 弍磦仍亠仆亳亠 仗仂亠亟 -- USE work.project_pkg; ENTITY reg_file IS GENERIC (...); PORT (...); END ENTITY n_reg; ARCHITECTURE rtl OF reg_file IS BEGIN PROCESS(...) BEGIN ... END PROCESS; ... END; PROCEDURE inc(a: INOUT INTEGER; step: INTEGER := 1) IS BEGIN a := a + step; END PROCEDURE inc; ... PACKAGE project_pkg IS ... PROCEDURE inc(a: INOUT INTEGER; step: INTEGER := 1); ... END PACKAGE project_pkg; PACKAGE BODY project_pkg IS END PACKAGE BODY project_pkg; ... ... 舒仍亳亳亠 仗仂仂亳仗舒 仗仂亟仗仂亞舒仄仄 仆亠仂弍磶舒亠仍仆仂, 仆仂 亠从仂仄亠仆亟亠
  • 5. 弌仗亳仂从 仗舒舒仄亠仂于 仗仂亠亟 PROCEDURE name[(parameter_interface_list)] IS ... ([CONSTANT|VARIABLE|SIGNAL] identifier {,}: [IN|OUT|INOUT] type_indication [:= expression] {;}) 仄/亟亠仆亳亳从舒仂 仗舒舒仄亠舒 仍舒 仗舒舒仄亠舒 (仄仂亢亠 弍 亠亠 FILE) 亳亟 仗舒舒仄亠舒 丐亳仗 仗舒舒仄亠舒 仆舒亠仆亳亠 仗仂 仄仂仍舒仆亳. 仂亢亠 弍 亰舒亟舒仆仂 仂仍从仂 亟仍 仗舒舒仄亠仂于 从仍舒舒 CONSTANT 亳 VARIABLE PROCEDURE foo(val: INTEGER) -- val - CONSTANT PROCEDURE foo(val: IN INTEGER) -- val - CONSTANT PROCEDURE foo(val, bar: OUT INTEGER) -- val, bar - VARIABLE PROCEDURE foo(val: INOUT INTEGER) -- val VARIABLE
  • 6. 亰仂于 仗仂亠亟 于 VHDL 亰仂于 仗仂亠亟 亰舒仗亳于舒亠 于 亳仂亟仆仂仄 从仂亟亠 从舒从 仂亟亠仍仆亶 仂仗亠舒仂, 从仂仂亶 亳仄亠亠 仍亠亟ﾑ亳亶 亳仆舒从亳: [label:] name [(parameter_list)]; 亠从舒 弌仗亳仂从 舒从亳亠从亳 仗舒舒仄亠仂于 ([parameter_name =>] expression|signal_name|variable_name|OPEN, {}) 个仂仄舒仍仆亶 仗舒舒仄亠 于舒 亳仗舒 仂仗仂舒于仍亠仆亳: 仄亠仆仂于舒仆仆仂亠 (=>) 仂亰亳亳仂仆仆仂亠 个舒从亳亠从亳亶 仗舒舒仄亠 舒亢亠仆亳亠/仂仆舒仆仆仂亠 亰仆舒亠仆亳亠 弌亳亞仆舒仍 亠亠仄亠仆仆舒 仍ﾑ亠于仂亠 仍仂于仂 OPEN - 仆亠 亳仗仂仍亰亠 亳仍亳 亰仆舒亠仆亳亠 仗仂 仄仂仍舒仆亳
  • 7. 仂亠亟 于 VHDL 仍亳 亳仗仂仍亰亠 仄亠舒仆仆亶 亳仗 仂仗仂舒于仍亠仆亳 仗舒舒仄亠仂于 仂亞亟舒, 亳仄亠仆仂于舒仆仆仂亠 仂仗仂舒于仍亠仆亳亠 于 仗亳从亠 仗舒舒仄亠仂于 亟仂仍亢仆仂 于亠亞亟舒 弍 仗仂仍亠亟仆亳仄: do_smth(good, more => 1, even_more => 2); do_smth(bad, more => 1, 2); -- 仆舒亠仆 仗仂磲仂从 舒舒仄亠-从仂仆舒仆 亳 仗舒舒仄亠-仗亠亠仄亠仆仆亠 仗亠亠亟舒ﾑ 于/亳亰 仗仂亠亟 仗仂 亰仆舒亠仆亳 亳 于亰仂于亠 仗仂亠亟 仗舒舒仄亠仂仄 亳亞仆舒仍仂仄 仗仂亳仂亟亳 仗亠亠亟舒舒 仗舒舒仄亠舒 仆亠 仗仂 亰仆舒亠仆亳, 舒 仗仂 仍从亠: 亰仆舒亠仆亳亠 亳亞仆舒仍舒 仄仂亢亠 仄亠仆 仆亠 仂仍从仂 于 亠亰仍舒亠 于仗仂仍仆磳仄 于 仗仂亠亟亠 亟亠亶于亳亶, 仆仂 亳 于 亠亰仍舒亠 亟亠亶于亳亶, 于仗仂仍仆磳仄 仗舒舒仍仍亠仍仆仂 仆亠亶 (亟亞亳仄亳 仗仂亠舒仄亳, 仗舒舒仍仍亠仍仆仄亳 仂仗亠舒仂舒仄亳)
  • 8. 仂亠亟 于 VHDL 仍亳 亳仗仂仍亰亠 仂仄舒仍仆亶 仗舒舒仄亠-亳亞仆舒仍 于亳亟舒 OUT, 仂 亳亰仄亠仆亠仆亳亠 亰仆舒亠仆亳 仂亞仂 仗舒舒仄亠舒 于 仗仂亠亟亠 于仍亠亠 亰舒 仂弍仂亶 亳亰仄亠仆亠仆亳亠 亰仆舒亠仆亳 仂仂于亠于ﾑ亠亞仂 亠仄 舒从亳亠从仂亞仂 仗舒舒仄亠舒 亳亞仆舒仍舒 于 于亰于舒于亠仄 仗仂亠亟 仗仂亠亠 个仂仄舒仍仆亠 仗舒舒仄亠-亳亞仆舒仍 舒从亢亠 仄仂亞 亳仄亠 于亳亟 INOUT. 仂仄 仍舒亠 于 从舒亠于亠 舒从亳亠从仂亞仂 仗舒舒仄亠舒 亟仂仍亢亠仆 于仗舒 亳亞仆舒仍, 于仆亠仆亳亶 从 仂弍亠从 仄仂亟亠仍亳仂于舒仆亳, 舒 仆亠 仂仗亳舒仆仆亶 于仆亳 仆亠亞仂 从舒亠于亠 从仍舒舒 (仂弍亠从舒) 仗舒舒仄亠舒 仄仂亞 于仗舒 FILE, 于 舒从仂仄 仍舒亠 于亳亟 仗舒舒仄亠舒 (IN, OUT, INOUT) 仆亠 从舒亰于舒亠: PROCEDURE writeline(FILE f: text; l: INOUT line);
  • 9. 仂亠亟 于 VHDL 仂弍亠仄 于亳亟亠 仗仂亠亟 磦仍ﾑ 束亳仆亠亰亳亠仄仄亳損, 亠仍亳 仂仆亳 仆亠 仂亟亠亢舒 于 于仂亠仄 亠仍亠 仂仗亠舒仂 WAIT: 亠仍亳 于 亠仍亠 仗仂亠亟 亳仗仂仍亰亠 仂仗亠舒仂 WAIT, 仂 于亰仂于 仗仂亠亟 亳亰 仆从亳亳 仆亠亟仂仗亳仄, 舒 于亰仂于 亳亰 亠仍舒 仂仗亠舒仂舒 PROCESS 于仂亰仄仂亢亠仆 于 仍舒亠, 亠仍亳 仂仗亠舒仂 PROCESS 仆亠 仂亟亠亢亳 仗亳从舒 于于亳亠仍仆仂亳 亠亠仄亠仆仆亠, 仂弍磦仍亠仆仆亠 于 仗仂亟仗仂亞舒仄仄亠 亳仆亳亳舒仍亳亰亳ﾑ 亰舒仆仂于仂 仗亳 从舒亢亟仂仄 于亰仂于亠 仗仂亠亟 仂亰仄仂亢亠仆 亠从亳于仆亶 于亰仂于 仗仂亠亟 仆亠 于亠亞亟舒 束亳仆亠亰亳亠晛 仂亰仄仂亢仆仂 亳仗仂仍亰仂于舒仆亳亠 仄亠舒仆亳亰仄舒 束仗亠亠亞亰从亳損 仗仂亠亟 于亰仂于 仂仂于亠于ﾑ亠亶 仂仗亠亟亠仍磳 亳仂亟 亳亰 仆舒弍仂舒 (从仂仍亳亠于舒) 亳 亳仗舒 舒从亳亠从亳 仗舒舒仄亠仂于
  • 10. 仂亠亟 于 VHDL CONSTANT VARIABLE ARCHITECTURE rtl OF example IS PROCEDURE inc(a: INOUT INTEGER; step: INTEGER := 1) IS BEGIN a := a + step; END PROCEDURE inc; BEGIN name : PROCESS IS VARIABLE v: INTEGER := 0; BEGIN REPORT "v = " & INTEGER'IMAGE(v) SEVERITY NOTE; inc(v); -- a := a + 1 v = 1 WAIT FOR 10 ns; inc(a => v, step => 2); -- a := a + 2 v = 3 WAIT FOR 10 ns; inc(v, step => 2 + 3); -- a := a + 2 + 3 v = 8 END PROCESS name; END ARCHITECTURE rtl;
  • 11. 仂亠亟 于 VHDL PROCEDURE convert(SIGNAL sel: IN BIT_VECTOR (0 TO 1); SIGNAL val : OUT BIT) IS BEGIN CASE sel IS WHEN "00" | "11" => val <= '1'; WHEN OTHERS => val <= '0'; END CASE; END PROCEDURE convert; ... convert(sel => addr, val => data); -- convert(addr, data); ... -- 亠舒仍亳亰舒亳 XNOR
  • 12. 仂亠亟 于 VHDL ARCHITECTURE rtl OF adder IS PROCEDURE addu(a, b: IN STD_LOGIC_VECTOR(N - 1 DOWNTO 0); signal res: OUT STD_LOGIC_VECTOR(N - 1 DOWNTO 0)) IS VARIABLE sum: STD_LOGIC_VECTOR(N - 1 DOWNTO 0); VARIABLE carry: STD_LOGIC := '0'; BEGIN FOR index IN sum'reverse_range LOOP sum(index) := a(index) XOR b(index) XOR carry; carry := (a(index) AND b(index)) OR (carry AND (a(index) XOR b(index))); END LOOP; result <= sum; END PROCEDURE addu; BEGIN addu(a => data_a, b => data_b, res => res); END ARCHITECTURE rtl; N = 1 N = 2
  • 13. 仂亠亟 于 VHDL ARCHITECTURE rtl OF adder IS PROCEDURE addu(a, b: IN STD_LOGIC_VECTOR(N - 1 DOWNTO 0); signal res: OUT STD_LOGIC_VECTOR(N - 1 DOWNTO 0)) IS ... -- 仄仂亳 仗亠亟亟亳亶 仍舒亶亟 BEGIN ... -- 仄仂亳 仗亠亟亟亳亶 仍舒亶亟 END PROCEDURE addu; BEGIN reg : PROCESS (clk) IS BEGIN IF rising_edge(clk) THEN addu(data_a, data_b, res); END IF; END PROCESS reg; END ARCHITECTURE rtl; N = 1 N = 2
  • 14. 仂亠亟 于 VHDL SIGNAL en: STD_LOGIC; ... convert(sel => addr, val => en); reg : PROCESS (clk, en) IS begin IF rising_edge(clk) THEN if en = '1' THEN addu(a => data_a, b => data_b, res => res); END IF; END IF; END PROCESS reg;
  • 15. 仂亠亟 于 VHDL 亠仍亠 仗仂亠亟 仄仂亢亠 亳仗仂仍亰仂于舒 仂仗亠舒仂 RETURN, 仆舒亰仆舒亠仆亳亠 从仂仂仂亞仂 亰舒于亠亠仆亳亠 于仗仂仍仆亠仆亳 仗仂亠亟: [label:] RETURN; PROCEDURE sort2(VARIABLE x1,x2: INOUT INTEGER) IS VARIABLE t: INTEGER; BEGIN IF x1 > x2 THEN RETURN; ELSE t := x1; x1 := x2; x2 := t; END IF; END PROCEDURE; 舒从 仂 亟亠仍舒 弍亠亰 亟仂仗仂仍仆亳亠仍仆仂亶 仗亠亠仄亠仆仆仂亶 "t"?
  • 16. 亠亠亞亰从舒 仗仂亠亟 -- 仗仂仂亳仗 仗仂亠亟 inc PROCEDURE inc (a: INOUT word32; by: IN word32 := X"000_0001"); PROCEDURE inc (a: INOUT STD_LOGIC_VECTOR; by: IN STD_LOGIC_VECTOR := X"000_0001"); -- 仂仄舒仍仆仄亳 仗舒舒仄亠舒仄亳 仄仂亞 于仗舒 仄舒亳于 -- 仆亠仂亞舒仆亳亠仆仆仂亶 亟仍亳仆, 仆仂 仗亳 于亰仂于亠 仗仂亠亟 亟仍 仆亳 -- 亟仂仍亢仆 弍 仂仗亠亟亠仍亠仆 舒从亳亠从亳亠 亰仆舒亠仆亳亠 于 仂亞仂 -- 仂亞舒仆亳亠仆仆仂仄 亟亳舒仗舒亰仂仆亠 PROCEDURE inc (a, b: IN STD_LOGIC_VECTOR; by: IN STD_LOGIC_VECTOR := X"000_0001"); PROCEDURE inc (a: INOUT INTEGER; by: IN INTEGER := 1); -- 仗仂亰亳亳仂仆仆仂亠 仂仗仂舒于仍亠仆亳亠, 于 亰舒于亳亳仄仂亳 仂 亳仗舒 -- 亟舒仆仆 count 弍亟亠 于亰于舒仆舒 仂仂于亠于ﾑ舒 仗仂亠亟舒 inc(count); -- 亳仄亠仆仂于舒仆仆仂亠 仂仗仂舒于仍亠仆亳亠 inc(a => count, by => open) inc(a => count)