狠狠撸

Greater San Diego Area United States

Staff ASIC Design Engineer

Telecom / Mobile

COMPUTER AIDED DESIGN SKILL Languages: VHDL, Verilog, System Verilog, Matlab, C/C++, Perl and SystemC. Design Tool: Modelsim (Mentor Graphics), ClearCase,DOORS, Debussy, Spyglass, Synopsys Design Analyzer, Flow3, Xilinx ISE, Chipscope, Active-HDL (Aldec), Quartus2 (Altera), Simplify Pro (Synplicity), Libero (Actel), Visual HDL (Innoveda), CoreGen (XILINX), FPGA Editor, VSS (Synopsys), Analog Artist (Cadence), Simulink, System Generator (Xilinx) Lab tools: Logic Analyzer, Pattern Generator and Oscilloscope.