Senior engineer with hands-on expertise in IC Physical design .Over 12 years of Industry experience involving Physical design, Chip and Block level Floor Planning, Place and Route(Semi custom ASIC), CTS, Timing Closure , Flow development and automation in tcl.
Proficient user of SOC encounter , Synopsys IC compiler and Magma flows. Expertise in the entire spectrum of the Place and Route Flow from Netlist to GDSII.Taped out multiple designs leading a group of engineers.
Proven ability to solve physical design problems and flow/tool issues
Excellent interpersonal and communication skills
Taped out chips till 16 nm.
ï‚• Chip and Block Level Floor Planning.
ï‚• Place and Route (Semi cust...