5.6 years of hands on experience with strong exposure on ASIC Design and Verification.
Exhaustive experience in RTL Design(SystemVerilog/Verilog/VHDL)
Experience on running STA analysis on full chip
Exp. in Formal Verification/Equivalence Checking
Exp. In Spyglass Lowpower for checking the voltage domine crossing violations
Exp. In Lint Checking for the Soc at RTL/GATE level using Spyglass
Good knowledge and Exposure on Synthesis
Experience in Performing Timing ECO鈥檚, Functional ECO鈥檚
Skill Set : C,Assembley,Verilog,System Verilog, VHDL, Perl
Protocols Worked :SPI,I2C,UART
Methodologies : VMM
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